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參數(shù)資料
| 型號： | LTC1401IS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 12BIT W/SHTDN 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 30mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
11
LTC1401
1401fa
APPLICATIONS INFORMATION
WU
U
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1401, a printed circuit board is
required. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital traces alongside an analog signal trace
or underneath the ADC. The analog input should be
screened by GND.
High quality tantalum and ceramic bypass capacitors
should be used at the VCC and VREF pins as shown in the
Typical Application on the first page of this datasheet. For
LTC1401 F09b
–
+
R2
10k
R9
20
R4
100k
R5
4.3k
FULL-SCALE
ADJUST
R3
100k
R6
400
R1
10k
ANALOG
INPUT
0V TO 2.048V
A1
3V
R8
10k
OFFSET
ADJUST
R7
100k
3V
AIN
LTC1401
optimum performance, a 10
F surface mount AVX capaci-
tor in parallel with a 0.1
Fceramicisrecommendedforthe
VCC and VREF pins. The capacitors must be located as close
to the pins as possible. The traces connecting the pins and
the bypass capacitors must be kept short and should be
made as wide as possible.
Input signal leads to AIN and signal return leads from GND
(Pin 4) should be kept as short as possible to minimize
noise coupling. In applications where this is not possible,
a shielded cable between the analog input signal and the
ADC is recommended. Also, any potential difference in
grounds between the analog signal and the ADC appears
as an error voltage in series with the analog input signal.
Attention should be paid to reducing the ground circuit
impedance as much as possible.
Figure 10 shows the recommended system ground con-
nections. All analog circuitry grounds should be termi-
nated at the LTC1401 GND pin. The ground return to the
power supply from Pin 4 should be low impedance for
noise free operation. Digital circuitry grounds must be
connected to the digital supply common.
Figure 9a. LTC1401 Full-Scale Adjust Circuit
LTC1401 F09a
–
+
R2
10k
R3
10k
R1
50
R4
100
FULL-SCALE
ADJUST
VIN
A1
LTC1401
AIN
GND
ADDITIONAL PINS OMITTED FOR CLARITY
±20LSB TRIM RANGE
Figure 9b. LTC1401 Offset and Full-Scale Adjust Circuit
Figure 10. Power Supply Connection
ANALOG SUPPLY
GND
3V
+
LTC1401
VCC
GND
DIGITAL SUPPLY
GND
3V
+
DIGITAL CIRCUITRY
VCC
GND
LTC1401 F10
Power-Down Mode
Upon power up, the LTC1401 is initialized to the active
state and is ready for conversion. However, the chip can be
easily placed into Nap or Sleep mode by exercising the
right combination of CLK and CONV signals. In Nap mode,
all power is off except the internal reference which remains
active and provides 1.20V output voltage to the other
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