參數(shù)資料
型號(hào)： LTC1401
廠商： Linear Technology Corporation
英文描述： Complete SO-8, 12-Bit, 200ksps ADC with Shutdown(SO-8封裝，12位,200ksps，模數(shù)轉(zhuǎn)換器（帶關(guān)斷）)
中文描述： 完整的SO - 8，12位，高達(dá)200ksps ADC的與關(guān)斷（以SO - 8封裝，12位，處理速度高達(dá)200ksps，模數(shù)轉(zhuǎn)換器（帶關(guān)斷））
文件頁(yè)數(shù)： 10/20頁(yè)
文件大小： 308K
代理商： LTC1401
10
LTC1401
APPLICATIO
S I
FOR
ATIO
U
is available at Pin 3 to provide up to 1mA current to an
external load. For minimum code transition noise, the
reference output should be decoupled with a capacitor to
filter wideband noise from the reference (10uF tantalum in
parallel with a 0.1uF ceramic is recommended). The V
REF
pin can be driven with a DAC or other means to provide
input span adjustment. The V
REF
pin must be driven to at
least 1.25V to prevent conflict with the internal reference.
The reference should not be driven to more than 3V.
Figure 6 shows an LT1360 op amp driving the reference
pin. Figure 7 shows a typical reference (LT1634-1.25)
connected to the LTC1401. This will provide improved
drift (equal to the maximum 25ppm/
°
C of the LT1634-
1.25) and a 2.1338V full scale.
W
U
U
UNIPOLAR OPERATION AND ADJUSTMENT
Figure 8 shows the ideal input/output characteristics for
the LTC1401. The code transitions occur midway between
successive integer LSB values (i.e., 0.5LSB, 1.5LSB,
2.5LSB, ... FS – 1.5LSB ). The output code is natural binary
with 1LSB = 2.048/4096 = 0.5mV.
Figure 7. Supplying a 2.5V Reference Voltage to
the LTC1401 with the LT1634-1.25
LTC1401 F06
–
+
V
REF(OUT)
≥
1.25V
A
IN
V
REF
GND
10
μ
F
3
INPUT RANGE
1.707 V
REF(OUT)
3V
LTC1401
LT1360
V
CC
LTC1401 F07
10
μ
F
3
INPUT RANGE 1.
(= 2.1338V)
LT1634-1.25
10V
V
IN
V
OUT
GND
3V
A
IN
V
REF
GND
LTC1401
V
CC
Figure 6. Driving the V
REF
with the LT1360 Op Amp
Figure 8. LTC1401 Unipolar Transfer Characteristics
INPUT VOLTAGE (V)
0V
O
FS – 1LSB
LTC1401 F08
111...111
111...110
111...101
111...100
000...000
000...001
000...010
000...011
1
LSB
UNIPOLAR
ZERO
1LSB =
FS
4096
2.048
4096
=
Unipolar Offset and Full-Scale Error Adjustments
In applications where absolute accuracy is important, the
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 9a
shows the extra components required for full scale error
adjustment. If both offset and full-scale adjustments are
needed, the circuit in Figure 9b can be used. For zero offset
error, apply 0.25mV (i.e., 0.5LSB) at the input and adjust
the offset trim until the LTC1401 output code flickers
between 0000 0000 0000 and 0000 0000 0001. For zero
full-scale error, apply an analog input of 2.04725V ( FS –
1.5LSB or last code transition ) at the input and adjust R5
until the LTC1401 output code flickers between 1111 1111
1110 and 1111 1111 1111.
相關(guān)PDF資料
PDF描述
LTC1402 Serial 12-Bit, 2.2Msps Sampling ADC with Shutdown(串行12位，2.2Msps 采樣模數(shù)轉(zhuǎn)換器(帶關(guān)斷))
LTC1404 Complete SO-8, 12-Bit, 600ksps ADC with Shutdown(SO-8封裝，12位,600ksps，模數(shù)轉(zhuǎn)換器（帶關(guān)斷）)
LTC1405 12-Bit, 5Msps, Sampling ADC(12位, 5Msps,采樣模數(shù)轉(zhuǎn)換器)
LTC1406 Low Power, 8-Bit, 20Msps, Sampling A/D Converter(低功耗,12位, 20Msps,采樣模數(shù)轉(zhuǎn)換器)
LTC1409 12-Bit, 800ksps Sampling A/D Converter with Shutdown(12位, 800ksps,采樣模數(shù)轉(zhuǎn)換器(帶關(guān)斷))
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