Input signal leads to AIN and signal return leads from GND (Pi" />
參數(shù)資料
型號(hào)： LTC1400IS8#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 4/20頁(yè)
文件大?。?/td> 0K
描述： IC A/D CONV 12BIT W/SHTDN 8-SOIC
標(biāo)準(zhǔn)包裝： 100
位數(shù)： 12
采樣率（每秒）： 400k
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 160mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOIC
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)單端，單極；1 個(gè)單端，雙極
產(chǎn)品目錄頁(yè)面： 1346 (CN2011-ZH PDF)
LTC1400
12
1400fa
Input signal leads to AIN and signal return leads from GND
(Pin 4) should be kept as short as possible to minimize
noisecoupling.Inapplicationswherethisisnotpossible,a
shielded cable between source and ADC is recommended.
Also,sinceanypotentialdifferenceingroundsbetweenthe
signalsourceandADCappearsasanerrorvoltageinseries
with the input signal, attention should be paid to reducing
the ground circuit impedance as much as possible.
APPLICATIO S I FOR ATIO
W
U
ANALOG SUPPLY
–5V
GND
5V
+
LTC1400
VSS
VCC
GND
DIGITAL SUPPLY
GND
5V
+
DIGITAL CIRCUITRY
VCC
GND
1400 F11
Figure11showstherecommendedsystemgroundconnec-
tions. All analog circuitry grounds should be terminated at
theLTC1400GNDpin.ThegroundreturnfromtheLTC1400
Pin 4 to the power supply should be low impedance for
noise free operation. Digital circuitry grounds must be
connected to the digital supply common.
InapplicationswheretheADCdataoutputsandcontrolsig-
nalsareconnectedtoacontinuouslyactivemicroprocessor
bus, it is possible to get errors in the conversion results.
These errors are due to feedthrough from the micropro-
cessor to the successive approximation comparator. The
problem can be eliminated by forcing the microprocessor
into a Wait state during conversion or by using three-state
buffers to isolate the ADC data bus.
Power-Down Mode
Upon power-up, the LTC1400 is initialized to the active
state and is ready for conversion. However, the chip can
be easily placed into the Nap or Sleep mode by exercising
the right combination of CLK and CONV signal. In the Nap
modeallpowerisoffexcepttheinternalreference,whichis
still active and provides 2.42V output voltage to the other
circuitry. In this mode, the ADC draws only 6mW of power
instead of 75mW (for minimum power, the logic inputs
must be within 500mV of the supply rails). The wake-up
time from the Nap mode to the active mode is 350ns.
Figure 11. Power Supply Connection
CLK
CONV
NAP
SLEEP
VREF
t1
t11
REFRDY
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS. REFRDY APPEARS AS A BIT IN THE DOUT WORD.
1400 F12
Figure 12. Nap Mode and Sleep Mode Waveforms
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