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參數(shù)資料
| 型號： | LTC1278-5ISW#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/DCONV SAMPLNG W/SHTDN24SOIC |
| 標準包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 150mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 24-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個單端，雙極 |
5
LTC1278
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve. The
deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 1/2LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: AIN must not exceed VDD or fall below VSS by more than 50mV for
specified accuracy. Therefore the minimum supply voltage for the unipolar
mode is 4.95V. The minimum for the bipolar mode is 4.75V, – 2.45V.
Note 12: The falling CONVST edge starts a conversion. If CONVST returns
high at a bit decision point during the conversion it can create small errors.
For best performance ensure that CONVST returns high either within 120ns
after conversion start (i.e., before the first bit decision) or after BUSY rises
(i.e., after the last bit test). See mode 1a and 1b (Figures 12 and 13) timing
diagrams.
TI I G CHARACTERISTICS
W U
The q indicates specifications which apply over the full operating
temperature range; all other limits and typicals TA = 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below VSS (ground for unipolar
mode) or above VDD, they will be clamped by internal diodes. This product
can handle input currents greater than 60mA below VSS (ground for
unipolar mode) or above VDD without latch-up.
Note 4: When these pin voltages are taken below VSS (ground for unipolar
mode), they will be clamped by internal diodes. This product can handle
input currents greater than 60mA below VSS (ground for unipolar mode)
without latch-up. These pins are not clamped to VDD.
Note 5: AVDD = DVDD = VDD = 5V, (VSS = – 5V for bipolar mode), fSAMPLE =
400kHz (LTC1278-4), 500kHz (LTC1278-5), tr = tf = 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for unipolar and
bipolar modes.
(Note 5)
TYPICAL PERFORMANCE CHARACTERISTICS
U
W
Integral Nonlinearity vs
Output Code
CODE
0
–1.0
INL
ERROR
(LSB)
–0.5
0
0.5
1.0
512 1024 1536 2048
LT1278 G1
2560 3072 3584 4096
fSAMPLE = 500kHz
CODE
0
–1.0
DNL
ERROR
(LSB)
–0.5
0
0.5
1.0
512 1024 1536 2048
LT1278 G2
2560 3072 3584 4096
fSAMPLE = 500kHz
Differential Nonlinearity vs
Output Code
INPUT FREQUENCY (Hz)
10k
0
EFFECTIVE
NUMBER
OF
BITS
S/(N
+
D)
(dB)
3
5
7
10
100k
1M
2M
LT1278 G4
1
4
6
9
12
11
62
56
74
68
8
2
fSAMPLE = 500kHz
NYQUIST
FREQUENCY
ENOBs and S/(N
+ D) vs
Input Frequency
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