參數(shù)資料
型號(hào)： LTC1196-2ACS8#TR
廠商： Linear Technology
文件頁(yè)數(shù)： 16/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 8BIT 1MHZ SHUTDOWN 8SOIC
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 8
采樣率（每秒）： 1M
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 50mW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOIC
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)差分，單極
LTC1196/LTC1198
23
119698fb
APPLICATIONS INFORMATION
3V VERSUS 5V PERFORMANCE COMPARISON
Table 1 shows the performance comparison between 3V
and 5V supplies. The power dissipation drops by a factor
of ve when the supply is reduced to 3V. The converter
slows down somewhat but still gives excellent performance
on a 3V rail. With a 3V supply, the LTC1196 converts in
1.6μs, samples at 450kHz, and provides a 500kHz linear-
input bandwidth.
Dynamic accuracy is excellent on both 5V and 3V. The
ADCs typically provide 49.3dB of 7.9 ENOBs of dynamic
accuracy at both 3V and 5V. The noise oor is extremely
low, corresponding to a transition noise of less than 0.1LSB.
DC accuracy includes ±0.5LSB total unadjusted error at
5V. At 3V, linearity error is ±0.5LSB while total unadjusted
error increases to ±1LSB.
Table 1. 5V/3V Performance Comparison
LTC1196-1
5V
3V
PDISS
50mW
10mW
Max fSMPL
1MHz
383kHz
Min tCONV
600ns
1.6μs
INL (Max)
0.5LSB
Typical ENOBs
7.9 at 300kHz
7.9 at 100kHz
Linear Input Bandwidth (ENOBs > 7)
1MHz
500kHz
LTC1198-1
PDISS
50mW
10mW
PDISS (Shutdown)
15μW
9μW
Max fSMPL
750kHz
287kHz
Min tCONV
600ns
1.6μs
INL (Max)
0.5LSB
Typical ENOBs
7.9 at 300kHz
7.9 at 100kHz
Linear Input Bandwidth (ENOBs > 7)
1MHz
500kHz
TYPICAL APPLICATIONS
PLD Interface Using the Altera EPM5064
The Altera EPM5064 has been chosen to demonstrate the
interface between the LTC1196 and a PLD. The EPM5064
is programmed to be a 12-bit counter and an equivalent
74HC595 8-bit shift register, as shown in Figure 12. The
circuit works as follows: bringing ENA HIGH makes the CS
output HIGH and the EN input LOW to reset the LTC1196
and disable the shift register. Bringing ENA LOW, the CS
output goes HIGH for one CLK cycle with every 12 CLK
cycles. The inverted signal, EN, of the CS output makes
the 8-bit data available on the B0-B7 lines. Figures 13 and
14 show the interconnection between the LTC1196 and
EPM5064 and the timing diagram of the signals between
these two devices. The CLK frequency in this circuit can
run up to fCLK(MAX) of the LTC1196.
1196/98 F12
DATA
CLK
12-BIT
CONVERTER
CS
ENA
EN
CLK
B0-B7
8-BIT
SHIFT REGISTER
CS
ENA
CLK
DATA
B0-B7
3, 14, 25, 36
EPM5064
CLK
33
23
34
35
1196/98 F13
VCC
+
–
DATA
1
37
38
39
40
41
42
44
9-13, 21,
31, 32, 43
CLK
B7
B0
ENA
–IN
GND
VCC
CLK
DOUT
+IN
CS
1
2
3
4
8
7
6
5
LTC1196
VREF
1μF
RESERVE PINS OF EPM5064:
2, 4-8,15-20, 22, 24, 26-30
Figure 12. An Equivalent Circuit of the EPM5064
Figure 13. Interfacing the LTC1196 to the Altera EMP5064 PLD
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