參數(shù)資料
型號(hào)： LTC1098L
廠商： Linear Technology Corporation
元件分類： 串行ADC
英文描述： Micropower Sampling 8-Bit I/O A/D Converters(3V，微功耗，采樣8位串行I/O模數(shù)轉(zhuǎn)換器)
中文描述： 微采樣8位I /辦公自動(dòng)化/ D轉(zhuǎn)換器（3V供電，微功耗，采樣8位串行的I / O模數(shù)轉(zhuǎn)換器）
文件頁(yè)數(shù)： 13/28頁(yè)
文件大?。?/td> 368K
代理商： LTC1098L
13
LTC1096/LTC1096L
LTC1098/LTC1098L
CLK
t
CYC
CS
B7*
B6
B5
B4
B3
B2
B1
B0
B1
B2
B3
B4
B5
B6
B7
NULL
BIT
Hi-Z
D
OUT
LTC1096/98 F01
POWER
DOWN
Hi-Z
t
suCS
t
WAKEUP
t
CONV
CLK
CS
t
CYC
POWER
DOWN
t
WAKEUP
B0
B1
B2
B3
B4
B5
B6
B7
Hi-Z
D
OUT
t
CONV
HI-Z
t
suCS
NULL
BIT
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.
(MSB)
(MSB)
Figure 1. LTC1096(L) Operating Sequence
U
S
A
O
PPLICATI
U
U
Power Down and Wake-Up Time
The LTC1096(L)/LTC1098(L) draw power when the CS pin
is low and shut themselves down when that pin is high. In
order to have a correct conversion result, a 10
μ
s wake-up
time must be provided from CS falling to the first falling
clock (CLK) after the first rising CLK for the LTC1096(L)
and from CS falling to the MSBF bit CLK falling for the
LTC1098(L) (see Operating Sequence). If the LTC1096(L)/
LTC1098(L) are running with clock frequency less than or
equal to 100kHz, the wake-up time is inherently provided.
Example
Two cases are shown at right to illustrate the relationship
among wake-up time, setup time and CLK frequency for
the LT1096(L).
In Case 1 the clock frequency is 100kHz. One clock cycle
is 10
μ
s which can be the wake-up time, while half of that
can be the setup time. In Case 2 the clock frequency is
50kHz, half of the clock cycle plus the setup time (=1
μ
s)
can be the wake-up time. If the CLK frequency is higher
Case 1. Timing Diagram
Case 2. Timing Diagram
CS
LTC1096/98 AI Ex.
CLK
NULL BIT
B7
t
WAKEUP
10μs
t
su
t
su
t
WAKEUP
D
OUT
CS
CLK
D
OUT
than 100kHz, Figure 1 shows the relationship between the
wake-up time and setup time.
The wake-up time is inherently provided for the LTC1098(L)
with setup time = 1
μ
s (see Figure 2).
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