![](http://datasheet.mmic.net.cn/Linear-Technology/LTC1063CSW-TRPBF_datasheet_97950/LTC1063CSW-TRPBF_11.png)
LTC1063
11
1063fa
VIN
VOUT
1063 F10
C
V–
V+
R
0.1
F
1
2
3
4
8
7
6
5
LTC1063
0.1
F
fCLK
20
10
2
πRC
≤
1
fCLK
Aliasing
Aliasing is an inherent phenomenon of sampled data filters
and it primarily occurs when the frequency of an input
signal approaches the sampling frequency. For the
LTC1063, an input signal whose frequency is in the range
of fCLK ±6% will generate an alias signal into the filter’s
passband and stopband. Table 4 shows details.
Example:
LTC1063, fCLK = 20kHz, fC = 200kHz,
fIN = (19.6kHz, 100mVRMS)
fALIAS = (400Hz, 3.16mVRMS)
An input RC can be used to attenuate incoming signals
close to the filter clock frequency (Figure 10). A Butterworth
passband response will be maintained if the value of the
input resistor follows Table 1.
Table 4. Aliasing Data
INPUT FREQUENCY
OUTPUT FREQUENCY
0.9995fCLK
0.0005 fCLK
0dB
0.995 fCLK
0.005 fCLK
0dB
0.99
fCLK
0.01
fCLK
–3
dB
0.9875fCLK
0.0125 fCLK
–10.2 dB
0.985 fCLK
0.015 fCLK
– 17.7 dB
0.9825fCLK
0.0175 fCLK
– 24.3 dB
0.98
fCLK
0.02
fCLK
–30
dB
0.975 fCLK
0.025 fCLK
–40
dB
0.97
fCLK
0.03
fCLK
–48
dB
0.965 fCLK
0.035 fCLK
– 54.5 dB
0.96
fCLK
0.04
fCLK
– 60.4 dB
0.955 fCLK
0.045 fCLK
– 65.5 dB
0.95
fCLK
0.05
fCLK
– 70.16 dB
0.94
fCLK
0.06
fCLK
– 78.25 dB
0.93
fCLK
0.07
fCLK
– 85.3 dB
0.9
fCLK
0.1
fCLK
– 100.3 dB
Figure 10. Adding an Input Anti-Aliasing RC
noise ratio at a given distortion level. The wideband noise
(
VRMS) is nearly independent of the value of the clock
frequency and excludes the clock feedthrough. The
LTC1063’s typical wideband noise is 95
VRMS. Figure 9
shows the same scope photo as Figure 8 but with a more
sensitive vertical scale: The clock feedthrough is imbed-
ded in the filter’s wideband noise. The peak-to-peak
wideband noise of the filter can be clearly seen; it is
approximately 500
VP-P. Note that 500VP-P equals the
95
VRMS wideband noise of the part, multiplied by a crest
factor or 5.25.
OUTPUT AMPLITUDE
REFERENCED TO
INPUT SIGNAL
2
s/DIV
1063 F08
fCLK = 100kHz, fC = 1kHz, VS = ±5V, 1MHz SCOPE BW
5mV/DIV
0.5mV/DIV
2
s/DIV
1063 F09
fCLK = 100kHz, fC = 1kHz, VS = ±5V, 1MHz SCOPE BW
Figure 8. LTC1063 Output Clock Feedthrough + Noise
Figure 9. LTC1063 Output Clock Feedthrough + Noise
APPLICATIO S I FOR ATIO
WU
UU