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參數(shù)資料
| 型號(hào)： | LT8415IDDB#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類(lèi)： | 穩(wěn)壓器 |
| 英文描述： | 0.03 A SWITCHING REGULATOR, PDSO12 |
| 封裝： | 3 X 2 MM, LEAD FREE, PLASTIC, DFN-12 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 182K |
| 代理商： | LT8415IDDB#TRPBF |
LT8415
10
8415f
APPLICATIONS INFORMATION
If the application doesn’t require the output disconnect
function, the CAP and VOUT pin can be shorted, and higher
power converter efciency can be achieved.
SHDN Pin Comparator and Hysteresis Current
An internal comparator compares the SHDN pin voltage
with an internal voltage reference (~1.3V) which gives a
precise turn-on voltage level. The internal hysteresis of this
turn-on voltage is about 60mV. When the chip is turned on,
and the SHDN pin voltage is close to this turn-on voltage,
0.1μA current ows out of the SHDN pin. This current is
called SHDN pin hysteresis current, and will go away when
the chip is off. By connecting the external resistors as in
Figure 2, a user-programmable enable voltage function
can be realized.
The turn-on voltage for the conguration is:
1.30 (1 + R1/R2)
and the turn-off voltage is:
(1.24 – R3 10–7) (1 + R1/R2) – R1 10–7
where R1, R2 and R3 are resistance value in Ω.
R1
ENABLE VOLTAGE
R2
R3
CONNECT TO
SHDN PIN
Figure 2. Programming Enable Voltage by Using External
Resistors
Board Layout Considerations
As with all switching regulators, careful attention must
be paid to the PCB layout and component placement. To
maximize efciency, switch rise and fall times are made
as short as possible. To prevent electromagnetic interfer-
ence (EMI) problems, proper layout of the high frequency
switching path is essential. The voltage signal of the SW pin
has sharp rising and falling edges. Minimize the length and
area of all traces connected to the SW pin and always use
a ground plane under the switching regulator to minimize
interplane coupling. In addition, the FBP pin and VREF pin
are sensitive to noise. Minimizing the length and area of all
traces to these two pins is recommended. Recommended
component placement is shown in Figure 3.
VIAS TO GROUND PLANE REQUIRED
TO IMPROVE THERMAL PERFORMANCE
VIAS FOR CAP AND VOUT GROUND RETURN THROUGH
SECOND METAL LAYER, CAPACITOR GROUNDS MUST
BE RETURNED DIRECTLY TO IC GROUND
8410 F03
SHDN
GND
SW
IN1
IN2
VCC
FBP
CAP
VREF
VOUT
OUT1
OUT2
GND
VIN
SHDN
IN2
IN1
OUT1
OUT2
Figure 3. Recommended Board Layout
Half-Bridge Control Signals
The half-bridge is controlled by the IN1 and IN2 pins. The
IN1 and IN2 pins should be driven with a logic signal.
When the chip is enabled, the OUT1 and OUT2 voltages
are equal to VOUT IN1 and IN2 are driven higher than 1V,
and they are near GND when IN1 and IN2 are driven below
0.3V. Do not drive the IN1 or IN2 pins between 0.3V to
1V for more than 20μs since this will leave OUT1 or OUT2
in an uncertain state and may also cause shoot-through
current.
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