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參數(shù)資料
| 型號： | LT8415IDDB#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.03 A SWITCHING REGULATOR, PDSO12 |
| 封裝： | 3 X 2 MM, LEAD FREE, PLASTIC, DFN-12 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 182K |
| 代理商： | LT8415IDDB#PBF |
LT8415
6
8415f
BLOCK DIAGRAM
PIN FUNCTIONS
SHDN(Pin1):ShutdownPin.Thispinisusedtoenable/dis-
able the chip. Drive below 0.3V to disable the chip. Drive
above 1.4V to activate the chip. Do not oat this pin.
VCC (Pin 2): Input Supply Pin. Must be locally bypassed
to GND. See typical applications section.
GND (Pin 3 and Pin 13): Ground. Tie directly to local
ground plane. Pin 13 is oating but must be grounded
for proper shielding.
SW (Pin 4): Switch Pin. This is the collector of the internal
NPN power switch. Minimize the metal trace area connected
to this pin to minimize EMI.
IN1 (Pin 5): First Half-Bridge Control Input. Do not oat
this pin.
IN2 (Pin 6): Second Half-Bridge Control Input. Do not
oat this pin.
OUT2 (Pin 7): Second Half-Bridge Output. This pin is
controlled in phase by the voltage on IN2. The output level
is either the voltage on VOUT or GND.
OUT1 (Pin 8): First Half-Bridge Output. This pin is controlled
in phase by the voltage on IN1. The output level is either
the voltage on VOUT or GND.
VOUT (Pin 9): Drain of Output Disconnect PMOS. Place a
bypass capacitor from this pin to GND.
CAP (Pin 10): This is the Cathode of the Internal Schottky
Diode. Place a bypass capacitor from this pin to GND.
VREF (Pin 11): Reference Pin. Soft start can be achieved
by placing a capacitor from this pin to GND. This cap
will be discharged for 70μs (typical) at the beginning
of start-up and then be charged to 1.235V with a 10μA
current source.
FBP(Pin 12): Positive Feedback Pin. This pin is the error
amplier’s positive input terminal. To achieve the desired
output voltage, choose the FBP pin voltage (VFBP) accord-
ing to the following formula:
VFBP = VOUT/31.85
When resistor divider from the VREF is used to set the FBP
voltage, choose the resistor divider ratio according to the
following formula:
R1/R2 = (39.33 – VOUT)/VOUT
For protection purposes, the output voltage can not exceed
40V even if VFBP is driven higher than VREF.
2
11
12
13
–
+
ENABLE
CHIP
1.235V
VREF
R1
R2
VCC
FBP
FB
VC
GND IN1
IN2
GND
400K
CAP
MAX
10μA
SW
OUT1
OUT2
SHDN
12.4M
VOUT
SWITCH
CONTROL
DISCHARGE
CONTROL
–
+
TIMING AND PEAK
CURRENT CONTROL
–
+
1
1.235V
3
9
10
4
OUTPUT DISCONNECT
CONTROL
1.235V
–
+
8415 BD
5
6
8
7
VOUT
TOP GATE
CONTROL
BOTTOM GATE
CONTROL
VOUT
TOP GATE
CONTROL
BOTTOM GATE
CONTROL
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