參數(shù)資料
型號(hào)： LT6556IUF#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 3/16頁(yè)
文件大?。?/td> 0K
描述： IC VIDEO MULTIPLEXER 2X1 24QFN
標(biāo)準(zhǔn)包裝： 2,500
功能： 視頻多路復(fù)用器
電路： 3 x 2:1
電壓電源： 雙電源
電壓 - 電源，單路/雙路(±)： ±2.25 V ~ 6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 24-QFN 裸露焊盤(pán)（4x4）
包裝： 帶卷 (TR)
LT6556
11
6556f
APPLICATIO S I FOR ATIO
WU
U
enabled output. However, since the disabled LT6556 and its
traces have around 6pF of capacitance, it may be desirable
to resistively isolate the outputs of each channel to maintain
at frequency response as shown in the graph labeled
“Maximum Capacitive Load vs Output Series Resistor” in
the Typical Performance Characteristics section.
ESD Protection
The LT6556 has reverse-biased ESD protection diodes on all
pins. If any pins are forced a diode drop above the positive
supply or a diode drop below the negative supply, large
currents may ow through these diodes. If the current is
kept below 10mA, no damage to the devices will occur.
TYPICAL APPLICATIO
U
RGB Multiplexer Demo Board
The DC892A Demo Board illustrates optimal routing,
bypassing and termination using the LT6556 as an
RGB video multiplexer. The schematic is shown in Figure 6.
All inputs and outputs are routed to have a characteristic
impedance of 75Ω and 75Ω input shunt and output series
terminations are connected as close to the part as pos-
sible. The board is fabricated with four layers with internal
ground and power planes.
While the 75Ω back termination resistors at the outputs
of the LT6556 minimize signal reections in the output
traces and isolate the part from any capacitive loading in
those traces, they also contribute to gain error if the out-
put is not terminated with high impedance. For example,
if the output is terminated with a 1k load, the 75Ω back
termination will cause a 7% gain error. Decreasing the
value of the back termination resistors will decrease the
signal attenuation but may compromise the AC response.
However, connecting the LT6556 output pins to the output
traces on the DC892A board without some series resistance
is not recommended; 10Ω to 20Ω is generally sufcient.
Figures 7 and 8 show the top and bottom side board layout
and placement.
Figure 6. Demo Board Schematic
5
IN1A
4
3
2
5
IN2A
4
3
2
5
IN3A
4
3
2
5
IN1B
4
3
2
5
IN2B
4
3
2
5
IN3B
4
3
2
IN1B
AGND1
IN3A
VREF
IN2A
DGND
IN1A
AGND2
6
7
8
9
4
5
3
2
1
24
23
22
14
13
12
11
10
15
16
17
18
19
20
21
V+
OUT2
V–
OUT1
IN3B
AGND3
IN2B
V–
V+
V–
OUT3
V+
SEL
EN
V+
U1 LT6556CUF
EXT
GND
1
3
2
JP5
VREF
JP12
BNC × 6
DGND
1
L1
Z = 75
JP13
JP14
JP5
JP6
JP7
J3
BANANA JACK
FLOAT
AGND
1
3
2
JP2
DGND
EXT
ENABLE
1
3
2
JP1
CONTROL
1
3
VCC
SEL A/B
AB
DGND
2
JP4
SEL
R7
20k
J1
50Ω BNC
EN
5432
1
R10
75Ω
R11
75Ω
R12
75Ω
R4
75Ω
R5
75Ω
R6
75Ω
2
DUAL
NOTE:
470pF BYPASS CAPACITORS LOCATED
AS CLOSE TO PINS AS POSSIBLE
SINGLE
AGND
JP3
SUPPLY
3
1
E1
EN
E4
SEL A/B
E2
DGND
E5
VREF
E3
AGND
R8
50Ω
OPT
Z = 50
EN
5
OUT1
J9
1
L2
Z = 75
R1
75Ω
R2
75Ω
R3
75Ω
Z = 75
1
J10
J11
J4
BANANA JACK
VEE
6556 F06
4
3
2
5
OUT2
4
3
2
5
OUT3
VEE
–3.3V TO –5V
4
3
2
C1
4700pF
C10
4700pF
C7
0.33μF
10V
C2
470pF
C3
470pF
C4
10μF
16V
1206
C9
10μF
16V
1206
J2
BANANA JACK
VCC
3.3V TO 5V
C5
4700pF
C6
470pF
C8
0.33μF
10V
BNC × 3
5432
1
R9
50Ω
OPT
J8
50Ω BNC
SEL A/B
V–
25
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