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參數(shù)資料
| 型號(hào)： | LT3585EDDB-2#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.95 A BATTERY CHARGE CONTROLLER, PDSO10 |
| 封裝： | 3 X 2 MM, LEAD FREE, PLASTIC, MO-229WECD-1, DFN-10 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大小： | 423K |
| 代理商： | LT3585EDDB-2#PBF |
LT3585-0/LT3585-1
LT3585-2/LT3585-3
10
3585f
OPERATIO
U
The LT3585 series of parts operate on the edge of dis-
continuous conduction mode. When CHRG/IADJ is driven
higher than 1.1V, the master latch is set. This enables the
part to deliver power to the photoash capacitor. When
the power switch, Q1, is turned on, current builds up in
the primary of the transformer. When the desired current
level is reached, the output of comparator A1 goes high,
resetting the switch latch that controls the state of Q1, and
the output of the DCM comparator goes low. Q1 now turns
off and the yback waveform on the SW node quickly rises
to a level proportional to VOUT. The secondary current ows
through high voltage diode(s), D1, and into the photoash
capacitor. When the secondary current decays to zero,
the voltage on the SW node collapses. When this voltage
reaches 130mV higher than VBAT, the output of A3 goes
high. This sets the switch latch and the power switch, Q1,
turns back on. This cycle repeats until the target VOUT level
is reached. When the target VOUT is reached, the master
latch resets and the DONE pin goes low.
The input current of an LT3585 series circuit can be
reduced by changing the voltage of the CHRG/IADJ pin.
When this pin is between 1.1V and 1.4V, a time delay is
added between when A3 goes high and the switch latch
is set, see Figure 2. If the part is enabled, and the CHRG/
IADJ pin is oated, internal circuitry drives the voltage on
the pin to 1.28V. This allows a single I/O port pin, which
can be three-stated, to enable or disable the part as well
as place the part into the input current reduction mode.
This feature effectively reduces the average input current
into the yback transformer. The magnitude of the delay
decreases with increasing VBAT. This causes the reduced
average input current to remain relatively at with changes
in VBAT. When CHRG/IADJ is brought higher than 1.6V,
no delay is added. The CHRG/IADJ pin functionality is
shown in Figure 3.
Both VBATandVINhaveundervoltagelockout(UVLO).When
one of these pins goes below its UVLO voltage, the DONE
pin goes low. With an insufcient bypass capacitor on VBAT
or VIN, the ripple on the pin is likely to activate UVLO and
terminate the charge. The applications circuits in the data
sheet suggest values adequate for most applications.
The LT3585 series also includes an integrated IGBT driver.
There are two output pins, IGBTPU and IGBTPD. The
IGBTPU pin is used to pull the gate of the IGBT up. This
should be done quickly to guarantee proper Xenon lamp
ignition. Tie this pin directly to the gate of the IGBT. The
IGBTPD pin is pinned out separately to allow for greater
exibility in choosing a series resistor between the pin and
the gate of the IGBT. This resistor can be used to slow
down the turn off of the IGBT.
IPRI
VSW
TIME
VSW
TIME
3585 F02
TIME
IPRI
TIME
Extra Delay Added
(~5.2
s at VBAT = 4.2V)
Normal Operation
CHRG/IADJ
≥ 1.6V
Reduced Input Current
CHRG/IADJ Three Stated
Figure 3. Basic Operation
Figure 2. Normal and Reduced Input Current Waveforms
VOUT
100V/DIV
DONE
2V/DIV
CHRG/IADJ
2V/DIV
LT3585-1
VBAT = 3.6V
COUT = 50F
*MUST TAKE CHRG/IADJ PIN ABOVE 1.1V, THEN FLOAT
1sec/DIV
<0.3V
3V
THREE
STATE*
CHRG/IADJ PIN STATE
3585 F03
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