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參數(shù)資料
| 型號： | LT3582EUD#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.72 A SWITCHING REGULATOR, PQCC16 |
| 封裝： | 3 X 3 MM, LEAD FREE, PLASTIC, MO-220WEED-2, QFN-16 |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 315K |
| 代理商： | LT3582EUD#TRPBF |
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LT3582/LT3582-5/LT3582-12
12
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All data bytes can be read from their assigned register
addresses. Since they share the same register addresses,
reads of the OTP and REG data bytes are differentiated
by their corresponding RSEL (Register Select) bits in the
CMDR register. All data written to register addresses 0-2 is
stored in REGO-REG2. Regardless of the RSEL bits, OTP
bytes cannot be written directly. See the OTP Programming
section for more information.
Data Transfer Protocol
The LT3582 series supports 8-bit data transfers in the
transaction formats shown in Figures 2 and 3. Multiple
data bytes can only be transferred by issuing multiple
transactions.
Figure 2 shows the required format for writing a byte of
data to the LT3582 series. Again, the chip address depends
on the CA pin logic state.
S
CHIP ADDR
W
A
REG ADDR
A
DATA
A
P
0110 001 OR
1000 101
0
00000b2:b0
0
b7:b0
0
FROM MASTER TO SLAVE
A: ACKNOWLEDGE (LOW)
FROM SLAVE TO MASTER
A: NOT ACKNOWLEDGE (HIGH)
R: READ BIT (HIGH)
W WRITE BIT (LOW)
S: START CONDITION
P: STOP CONDITION
Figure 2. I2C Byte Write Transaction
A byte of data is read from the LT3582 series using the
format shown in Figure 3. This transaction requires four I2C
bytes to read one byte of chip data and must be repeated
for each subsequent byte of data that is read.
S
CHIP ADDR
W
A
REG ADDR
A
0110 001 OR
1000 101
0
00000b2:b0
0
LT3582 Chip Conguration
Settings such as output voltages and sequencing are
digitally programmable. The chip uses settings from either
the REG or OTP bytes, depending on the states of the
corresponding RSEL bits (0 for OTP and 1 for REG).
During shutdown the RSEL bits are reset low. As a result,
the initial conguration comes from the OTP data bytes.
After power-up, the conguration can be changed by writing
new settings to the appropriate REG data byte(s) then
setting the corresponding RSEL bit(s).
Finally, data in the REG bytes can be permanently
programmed to OTP by applying voltage to the VPP pin
and setting the WOTP bit in the Command Register. See
the
OTP Programming section for more information.
LT3582-5/LT3582-12 Chip Conguration
The LT3582-5/LT3582-12 are shipped from the factory with
the OTP memory pre-programmed and LOCKed which
prohibits subsequent changes to the conguration. The
conguration can still be read through the I2C bus and
the RST and SWOFF bits of the CMDR register (described
later) are functional. The following sections describe the
various congurable features of the LT3582. The LT3582-5
and LT3582-12 are pre-congured as follows: VP and VN
are programmed for ±5V or ±12V respectively, LOCK = 1,
IRMP = 00, PDDIS = 1, PUSEQ = 11 and VPLUS may be 1
or 0. Since LOCK = 1, subsequent conguration changes
are prohibited. See
Conguration Lockout (LOCK Bit) for
more information.
Registers and OTP
The registers and OTP bytes for the LT3582 series are
organized as shown in Table 1. The CMDR is reset to 00h
upon power-up, during shutdown and during undervoltage
and thermal lockouts.
REG0-REG2 are never reset and must
always be loaded with valid data before use. The LT3582’s
OTP memory is shipped with all 0’s, and as a result, the
PUSEQ bits are congured to disable the outputs. The
PUSEQ bits must be recongured to enable the outputs.
APPLICATIONS INFORMATION
S
CHIP ADDR
R
A
DATA
A
P
0110 001 OR
1000 101
1
0
b7:b0
1
Figure 3. I2C Byte Read Transaction
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| LT3582EUD-12#TRPBF | 0.72 A SWITCHING REGULATOR, PQCC16 |
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