參數(shù)資料
型號(hào)： LT3574IMS#TRPBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： 1.1 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PDSO16
封裝： LEAD FREE, PLASTIC, MSOP-16
文件頁(yè)數(shù)： 6/24頁(yè)
文件大?。?/td> 285K
代理商： LT3574IMS#TRPBF
LT3574
3574f
applications inForMation
Setting the Current Limit Resistor
The maximum current limit can be set by placing a resistor
between the RILIM pin and ground. This provides some
flexibilityinpickingstandardoff-the-shelftransformersthat
may be rated for less current than the LT3574’s internal
power switch current limit. If the maximum current limit
is needed, use a 10k resistor. For lower current limits, the
following equation sets the approximate current limit:
R
A I
k
ILIM
LIM
=
+
65 10 0 9
10
3
( .
)
The Switch Current Limit vs RILIM plot in the Typical Per-
formance Characteristics section depicts a more accurate
current limit.
Undervoltage Lockout (UVLO)
The SHDN/UVLO pin is connected to a resistive voltage
divider connected to VIN as shown in Figure 8. The voltage
threshold on the SHDN/UVLO pin for VIN rising is 1.22V.
To introduce hysteresis, the LT3574 draws 2.5A from the
SHDN/UVLOpinwhenthepinisbelow1.22V.Thehysteresis
is therefore user-adjustable and depends on the value of
R1. The UVLO threshold for VIN rising is:
V
V R R
R
A R
IN UVLO RISING
(
,
)
.
(
)
.
=
+
1 22
1
2
2 5
1
The UVLO threshold for VIN falling is:
V
V R R
R
IN UVLO FALLING
(
,
)
.
(
)
=
+
1 22
1
2
To implement external run/stop control, connect a small
NMOS to the UVLO pin, as shown in Figure 8. Turning the
NMOS on grounds the UVLO pin and prevents the LT3574
from operating, and the part will draw less than a 1A of
quiescent current.
Minimum Load Requirement
The LT3574 obtains output voltage information through
thetransformerwhilethesecondarywindingisconducting
current. During this time, the output voltage (multiplied
times the turns ratio) is presented to the primary side of
the transformer. The LT3574 uses this reflected signal to
regulate the output voltage. This means that the LT3574
must turn on every so often to sample the output voltage,
which delivers a small amount of energy to the output.
This sampling places a minimum load requirement on the
output of 1% to 2% of the maximum load.
BIAS Pin Considerations
For applications with an input voltage less than 15V, the
BIAS pin is typically connected directly to the VIN pin. For
input voltages greater than 15V, it is preferred to leave the
BIAS pin separate from the VIN pin. In this condition, the
BIAS pin is regulated with an internal LDO to a voltage of
3V.BykeepingtheBIASpinseparatefromtheinputvoltage
at high input voltages, the physical size of the capacitors
can be minimized (the BIAS pin can then use a 6.3V or
10V rated capacitor).
Figure 8. Undervoltage Lockout (UVLO)
LT3574
SHDN/UVLO
GND
R2
R1
VIN
3574 F08
RUN/STOP
CONTROL
(OPTIONAL)
相關(guān)PDF資料
PDF描述
LT3579EUFD#PBF SWITCHING REGULATOR, PQCC20
LT3579IUFD-1#TRPBF SWITCHING REGULATOR, PQCC20
LT3579IFE#PBF SWITCHING REGULATOR, PDSO20
LT3579IFE-1#TRPBF SWITCHING REGULATOR, PDSO20
LT3579EUFD-1#TRPBF SWITCHING REGULATOR, PQCC20
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