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參數(shù)資料
| 型號(hào)： | LT3495BEDDB#TRMPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.78 A SWITCHING REGULATOR, PDSO10 |
| 封裝： | 3 X 2 MM, LEAD FREE, PLASTIC, MO-229WECD-1, DFN-10 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 299K |
| 代理商： | LT3495BEDDB#TRMPBF |
LT3495/LT3495B/
LT3495-1/LT3495B-1
12
3495b1b1fa
APPLICATIONS INFORMATION
Figure 6. Recommended Board Layout
can be set by the value of RCTRL and CCTRL. The following
expression can be used to design the soft-start time:
TSTART UP =RCTRL CCTRL In
V
SHDN
V
SHDN
– 1.235
where VSHDN is the voltage at SHDN pin when the part is
enabled. To ensure soft-start will work, the initial voltage
at CTRL pin when the part is enabled should be close to
0V. The soft-start may not work if this initial condition is
not satised.
Output Disconnect
The LT3495 series has an output disconnect PMOS that
blocks the load from the input during shutdown. During
normal operation, the maximum current through the PMOS
is limited by circuitry inside the chip. When the CAP and
VOUT voltage difference is more than 8.7V (typ), the cur-
rent through the PMOS is no longer limited, and can be
much higher. As a result, forcing 8.7V or higher voltage
from the CAP to the VOUT pins can damage the PMOS.
In cases when the CAP voltage is high and/or a large ca-
pacitor is used at the CAP pin, shorting VOUT to GND can
cause large PMOS currents to ow. Under this condition,
the PMOS peak current should be kept at less than 1A.
Also be aware of the thermal dissipation in the PMOS at
all times. In addition, if the input voltage is more than 8V,
the PMOS will turn on during shutdown, resulting in the
output voltage no longer being blocked from the input.
Under this condition, the output voltage will be about 8V
lower than the input voltage.
Board Layout Considerations
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
To maximize efciency, switch rise and fall times are made
as short as possible. To prevent electromagnetic interfer-
ence (EMI) problems, proper layout of the high frequency
switching path is essential. The voltage signal of the
SW pin has sharp rising and falling edges. Minimize the
length and area of all traces connected to the SW pin and
always use a ground plane under the switching regulator
to minimize interplane coupling. In addition, the FB pin
feeds into the internal error amplier and is sensitive to
noise. Minimizing the length and area of all traces to this
pin is recommended. Connect the feedback resistor R1
directly from the VOUT pin to the FB pin and keep the trace
as short as possible. Recommended component placement
is shown in Figure 6.
GND
VCC
CTRL
SHDN
SW
CAP
VOUT
FB
GND
CTRL
VIAS TO GROUND PLANE REQUIRED
TO IMPROVE THERMAL PERFORMANCE
VIAS FOR CAP GROUND RETURN THROUGH
SECOND METAL LAYER, CAPACITOR GROUNDS
MUST BE RETURNED DIRECTLY TO IC GROUND
SHDN
3495 F06
GND
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相關(guān)代理商/技術(shù)參數(shù) |
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| LT3495EDDB#TRPBF | 功能描述:IC REG BOOST ADJ 0.65A 10DFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 開關(guān)穩(wěn)壓器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:升壓（升壓） 輸出類型:可調(diào)式 輸出數(shù):1 輸出電壓:1.24 V ~ 30 V 輸入電壓:1.5 V ~ 12 V PWM 型:電流模式，混合 頻率 - 開關(guān):600kHz 電流 - 輸出:500mA 同步整流器:無 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:8-SOIC |
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