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參數(shù)資料
| 型號： | LT1959I |
| 廠商： | Linear Technology Corporation |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | RADIATION HARDENED HIGH EFFICIENCY, 5 AMP SWITCHING REGULATORS |
| 中文描述： | 抗輻射高效，5安培開關穩(wěn)壓器 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 292K |
| 代理商： | LT1959I |
18
LT1959
APPLICATIO
S I
FOR
ATIO
U
formulas show how to calculate each of these losses.
These formulas assume continuous mode operation, so
they should not be used for calculating efficiency at light
load currents.
Switch loss:
W
U
U
P
R
V
V
ns I
V
f
SW
SW OUT
OUT
IN
OUT
IN
=
) (
)
+
(
)( )( )
2
24
Boost current loss:
P
V
I
V
BOOST
OUT
OUT
IN
=
(
)
2
50
/
Quiescent current loss:
P
V
V
V
V
Q
IN
OUT
OUT
IN
=
(
)
+
(
)
+
(
)
0 001
0 005
0 002
2
R
SW
= Switch resistance (
≈
0.07)
24ns = Equivalent switch current/voltage overlap time
f = Switch frequency
Example: with V
IN
= 10V, V
OUT
= 5V and I
OUT
= 3A:
P
W
P
W
P
W
SW
BOOST
Q
=
(
)( ) ( )
+
10
0 36
2
/
( )( )
=
+
=
=
( ) (
)
=
=
(
)
+
(
)
+
( ) (
)
=
0 07 3
.
5
24 10
3 10 500 10
0 32
.
068
.
5
3 50
10
0 15
.
10 0 001
5 0 005
.
5
0 002
.
10
0 04
.
2
9
3
2
.
.
Total power dissipation is 0.68 + 0.15 + 0.04 = 0.87W.
Thermal resistance for LT1959 package is influenced by
the presence of internal or backside planes. With a full
plane under the SO package, thermal resistance will be
about 80
°
C/W. No plane will increase resistance to about
120
°
C/W. To calculate die temperature, use the proper
thermal resistance number for the desired package and
add in worst-case ambient temperature:
T
J
= T
A
+
θ
JA
(P
TOT
)
With the SO-8 package (
θ
JA
= 80
°
C/W), at an ambient
temperature of 50
°
C,
T
J
= 50 + 80 (0.87) = 120
°
C
Die temperature is highest at low input voltage, so use
lowest continuous input operating voltage for thermal
calculations.
FREQUENCY COMPENSATION
Loop frequency compensation of switching regulators
can be a rather complicated problem because the reactive
components used to achieve high efficiency also
introduce multiple poles into the feedback loop. The
inductor and output capacitor on a conventional step-
down converter actually form a resonant tank circuit that
can exhibit peaking and a rapid 180
°
phase shift at the
resonant frequency. By contrast, the LT1959 uses a “cur-
rent mode” architecture to help alleviate phase shift cre-
ated by the inductor. The basic connections are shown in
Figure 9. Figure 10 shows a Bode plot of the phase and gain
of the power section of the LT1959, measured from the V
C
pin to the output. Gain is set by the 5.3A/V transconduc-
tance of the LT1959 power section and the effective
complex impedance from output to ground. Gain rolls off
smoothly above the 600Hz pole frequency set by the
100
μ
F output capacitor. Phase drop is limited to about
70
°
. Phase recovers and gain levels off at the zero fre-
quency (
≈
16kHz) set by capacitor ESR (0.1
).
Figure 9. Model for Loop Response
–
+
1.21V
V
SW
V
C
LT1959
GND
1959 F09
R1
OUTPUT
ESR
C
F
C
C
R
C
ERROR
AMPLIFIER
FB
R2
C1
CURRENT MODE
POWER STAGE
g
m
= 5.3A/V
+
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