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參數(shù)資料
| 型號： | LT1641IS8#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 192K |
| 描述： | IC CTRLR HOTSWAP POS VOLT 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 9 V ~ 80 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
8
LT1641
1641fd
V
CC
TIMER
SENSE GATE
8
7
6
5
4
2
1
3
D1
CMPZ
5248B
GND
PWRGD
PWRGD
FB
R5
10&
5%
ON
R1
49.9k
1%
V
IN
24V
SHORT
PIN
GND
1641 F05
R2
3.4k
1%
C2
0.68礔
R6,
1k, 5%
R
S
0.025&
C1
10nF
R3
59k
1%
R4
3.57k
1%
R7
24k
5%
+
C
L
V
OUT
LT1641
Q1
IRF530
Figure 5. Typical Application
Figure 6. Power-Up Waveforms
APPLICATIO S I FOR ATIO
U
U
U
To prevent excessive power dissipation in the pass tran-
sistor and to prevent voltage spikes on the input supply
during short-circuit conditions at the output, the current
folds back as a function of the output voltage, which is
sensed at the FB pin (Figure 7).
When the voltage at the FB pin is 0V, the current limit
circuit drives the GATE pin to force a constant 12mV drop
across the sense resistor. As the output voltage at the FB
pin increases, the voltage across the sense resistor in-
creases until the FB pin reaches 0.5V, at which point the
voltage across the sense resistor is held constant at 47mV.
The maximum current limit is calculated as:
I
LIMIT
= 47mV/R
SENSE
For a 0.025& sense resistor, the current limit is set at
1.88A and folds back to 480mA when the output is shorted
to ground.
The LT1641 also features a variable overcurrent response
time. The time required for the chip to regulate the GATE
pin (Pin 6) voltage is a function of the voltage across the
sense resistor connected between the V
CC
pin (Pin 8) and
the SENSE pin (Pin 7). The larger the voltage, the faster the
gate will be regulated. Figure 8 shows the response time
as a function of overdrive at the SENSE pin.
TIMER
The TIMER pin (Pin 5) provides a method for program-
ming the maximum time the chip is allowed to operate in
current limit. When the current limit circuitry is not active,
the TIMER pin is pulled to GND by a 3礎(chǔ) current source.
After the current limit circuit becomes active, an 80礎(chǔ) pull-
up current source is connected to the TIMER pin and the
voltage will rise with a slope equal to 77礎(chǔ)/C
TIMER
as long
as the current limit circuit remains active. Once the desired
maximum current limit time is set, the capacitor value is:
C(nF) = 62 " t(ms).
If the current limit circuit turns off, the TIMER pin will be
discharged to GND by the 3礎(chǔ) current source.
Whenever the TIMER pin reaches 1.233V, the GATE pin is
immediately pulled to GND and the TIMER pin is pulled
back to GND by the 3礎(chǔ) current source. The part is not
allowed to turn on again until the voltage at the TIMER pin
falls below 0.5V.
The waveform in Figure 9 shows how the output turns off
following a short-circuit. The drop across the sense resis-
tor is held at 12mV as the timer ramps up. Since the output
did not rise bringing FB above 0.5V, the circuit turns off.
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| LT1671CMS8 | 功能描述:IC COMPARATOR 60NS LOW PWR 8MSOP RoHS:否 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:- 類型:帶電壓基準(zhǔn) 元件數(shù):4 輸出類型:CMOS，開路漏極，TTL 電壓 - 電源，單路/雙路(±):2 V ~ 11 V，±1 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:10mV @ 5V 電流 - 輸入偏壓（最小值）:- 電流 - 輸出（標(biāo)準(zhǔn)）:0.015mA @ 5V 電流 - 靜態(tài)（最大值）:8.5µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:12µs 磁滯:50mV 工作溫度:0°C ~ 70°C 封裝/外殼:16-DIP（0.300"，7.62mm） 安裝類型:通孔 包裝:管件 |
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