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    參數(shù)資料
    型號(hào): LT1364
    廠商: Linear Technology Corporation
    英文描述: Dual and Quad 70MHz, 1000V/us Op Amps
    中文描述: 雙核和四70MHz的,1000V/us運(yùn)算放大器
    文件頁(yè)數(shù): 10/12頁(yè)
    文件大?。?/td> 265K
    代理商: LT1364
    10
    LT1364/LT1365
    a comparator, peak detector or other open-loop applica-
    tion with large, sustained differential inputs
    . Under
    normal, closed-loop operation, an increase of power dis-
    sipation is only noticeable in applications with large slewing
    outputs and is proportional to the magnitude of the
    differential input voltage and the percent of the time that
    the inputs are apart. Measure the average supply current
    for the application in order to calculate the power dissipa-
    tion.
    Capacitive Loading
    The LT1364/LT1365 are stable with any capacitive load.
    This is accomplished by sensing the load induced output
    pole and adding compensation at the amplifier gain node.
    As the capacitive load increases, both the bandwidth and
    phase margin decrease so there will be peaking in the
    frequency domain and in the transient response as shown
    in the typical performance curves. The photo of the small
    signal response with 200pF load shows 62% peaking. The
    large signal response shows the output slew rate being
    limited to 10V/
    μ
    s by the short-circuit current. Coaxial
    cable can be driven directly, but for best pulse fidelity a
    resistor of value equal to the characteristic impedance of
    the cable (i.e., 75
    ) should be placed in series with the
    output. The other end of the cable should be terminated
    with the same value resistor to ground.
    Circuit Operation
    The LT1364/LT1365 circuit topology is a true voltage
    feedback amplifier that has the slewing behavior of a
    current feedback amplifier. The operation of the circuit can
    be understood by referring to the simplified schematic.
    The inputs are buffered by complementary NPN and PNP
    emitter followers which drive a 500
    resistor. The input
    voltage appears across the resistor generating currents
    which are mirrored into the high impedance node. Comple-
    mentary followers form an output stage which buffers the
    gain node from the load. The bandwidth is set by the input
    resistor and the capacitance on the high impedance node.
    The slew rate is determined by the current available to
    charge the gain node capacitance. This current is the
    differential input voltage divided by R1, so the slew rate is
    proportional to the input. Highest slew rates are therefore
    seen in the lowest gain configurations. For example, a 10V
    APPLICATIO
    S I
    FOR
    ATIO
    U
    W
    U
    U
    output step in a gain of 10 has only a 1V input step,
    whereas the same output step in unity gain has a 10 times
    greater input step. The curve of Slew Rate vs Input Level
    illustrates this relationship. The LT1364/LT1365 are tested
    for slew rate in a gain of –2 so higher slew rates can be
    expected in gains of 1 and –1, and lower slew rates in
    higher gain configurations.
    The RC network across the output stage is bootstrapped
    when the amplifier is driving a light or moderate load and
    has no effect under normal operation. When driving a
    capacitive load (or a low value resistive load) the network
    is incompletely bootstrapped and adds to the compensa-
    tion at the high impedance node. The added capacitance
    slows down the amplifier which improves the phase
    margin by moving the unity-gain frequency away from the
    pole formed by the output impedance and the capacitive
    load. The zero created by the RC combination adds phase
    to ensure that even for very large load capacitances, the
    total phase lag can never exceed 180 degrees (zero phase
    margin) and the amplifier remains stable.
    Power Dissipation
    The LT1364/LT1365 combine high speed and large output
    drive in small packages. Because of the wide supply
    voltage range, it is possible to exceed the maximum
    junction temperature under certain conditions. Maximum
    junction temperature (T
    J
    ) is calculated from the ambient
    temperature (T
    A
    ) and power dissipation (P
    D
    ) as follows:
    LT1364CN8: T
    J
    = T
    A
    + (P
    D
    x 130
    °
    C/W)
    LT1364CS8: T
    J
    = T
    A
    + (P
    D
    x 190
    °
    C/W)
    LT1365CN: T
    J
    = T
    A
    + (P
    D
    x 110
    °
    C/W)
    LT1365CS: T
    J
    = T
    A
    + (P
    D
    x 150
    °
    C/W)
    Worst case power dissipation occurs at the maximum
    supply current and when the output voltage is at 1/2 of
    either supply voltage (or the maximum swing if less than
    1/2 supply voltage). For each amplifier P
    DMAX
    is:
    P
    DMAX
    = (V
    +
    – V
    )(I
    SMAX
    ) + (V
    +
    /2)
    2
    /R
    L
    Example: LT1365 in S16 at 70
    °
    C, V
    S
    =
    ±
    5V, R
    L
    = 150W
    P
    DMAX
    = (10V)(8.4mA) + (2.5V)
    2
    /150
    = 126mW
    T
    JMAX
    = 70
    °
    C + (4 x 126mW)(150
    °
    C/W) = 145
    °
    C
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