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參數(shù)資料
| 型號： | LT1359CN#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 0K |
| 描述： | IC OP-AMP HI-SPD 25MHZ QUAD14DIP |
| 標準包裝： | 25 |
| 系列： | C-Load™ |
| 放大器類型： | 電壓反饋 |
| 電路數(shù)： | 4 |
| 轉(zhuǎn)換速率： | 600 V/µs |
| 增益帶寬積： | 25MHz |
| 電流 - 輸入偏壓： | 120nA |
| 電壓 - 輸入偏移： | 200µV |
| 電流 - 電源： | 2mA |
| 電流 - 輸出 / 通道： | 30mA |
| 電壓 - 電源，單路/雙路(±)： | ±2.5 V ~ 15 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 14-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 14-PDIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1318 (CN2011-ZH PDF) |
10
LT1358/LT1359
135859fb
Layout and Passive Components
The LT1358/LT1359 amplifiers are easy to use and toler-
ant of less than ideal layouts. For maximum performance
(for example, fast 0.01% settling) use a ground plane,
short lead lengths, and RF-quality bypass capacitors
(0.01
F to 0.1F). For high drive current applications use
low ESR bypass capacitors (1
F to 10F tantalum).
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input combine with the
input capacitance to form a pole which can cause peaking
or oscillations. If feedback resistors greater than 5k are
used, a parallel capacitor of value
CF > RG x CIN / RF
should be used to cancel the input pole and optimize
dynamic performance. For unity-gain applications where
a large feedback resistor is used, CF should be greater than
or equal to CIN.
Capacitive Loading
The LT1358/LT1359 are stable with any capacitive load.
As the capacitive load increases, both the bandwidth and
phase margin decrease so there will be peaking in the
frequency domain and in the transient response. Coaxial
cable can be driven directly, but for best pulse fidelity a
resistor of value equal to the characteristic impedance of
the cable (i.e., 75
) should be placed in series with the
output. The other end of the cable should be terminated
with the same value resistor to ground.
Input Considerations
Each of the LT1358/LT1359 inputs is the base of an NPN
and a PNP transistor whose base currents are of opposite
polarity and provide first-order bias current cancellation.
Because of variation in the matching of NPN and PNP beta,
the polarity of the input bias current can be positive or
negative. The offset current does not depend on NPN/PNP
beta matching and is well controlled. The use of balanced
source resistance at each input is recommended for
applications where DC accuracy must be maximized.
The inputs can withstand transient differential input volt-
ages up to 10V without damage and need no clamping or
source resistance for protection. Differential inputs, how-
ever, generate large supply currents (tens of mA) as
required for high slew rates. If the device is used with
sustained differential inputs, the average supply current
will increase, excessive power dissipation will result and
the part may be damaged. The part should not be used
as a comparator, peak detector or other open-loop
application with large, sustained differential inputs.
Under normal, closed-loop operation, an increase of power
dissipation is only noticeable in applications with large
slewing outputs and is proportional to the magnitude of
the differential input voltage and the percent of the time
that the inputs are apart. Measure the average supply
current for the application in order to calculate the power
dissipation.
APPLICATIO S I FOR ATIO
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