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參數(shù)資料
| 型號： | LT1024CN#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PREC OP-AMP UNVRSL DUAL 14DIP |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 2 |
| 轉(zhuǎn)換速率： | 0.2 V/µs |
| 電流 - 輸入偏壓： | 30pA |
| 電壓 - 輸入偏移： | 20µV |
| 電流 - 電源： | 380µA |
| 電壓 - 電源，單路/雙路(±)： | 2.4 V ~ 40 V，±1.2 V ~ 20 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 14-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 14-PDIP |
| 包裝： | 管件 |
8
LT1024
1024fa
Achieving Picoampere/Microvolt Performance
In order to realize the picoampere/microvolt level
accuracy of the LT1024, proper care must be exercised.
For example, leakage currents in circuitry external to the
op amp can significantly degrade performance. High qual-
ity insulation should be used (e.g., Teflon, Kel-F); clean-
ing of all insulating surfaces to remove fluxes and other
residues will probably be required. Surface coating may be
necessary to provide a moisture barrier in high humidity
environments.
Board leakage can be minimized by encircling the input
circuitry with a guard ring operated at a potential close to
that of the inputs: in inverting configurations, the guard
ring should be tied to ground; in noninverting connec-
tions, to the inverting input. Guarding both sides of the
printed circuit board is required. Bulk leakage reduction
depends on the guard ring width. Nanoampere level leak-
age into the offset trim terminals can affect offset voltage
and drift with temperature.
Microvolt level error voltages can also be generated in the
external circuitry. Thermocouple effects, caused by tem-
perature gradients across dissimilar metals at the con-
tacts to the input terminals, can exceed the inherent drift
of the amplifier. Air currents over device leads should be
minimized, package leads should be short, and the two
input leads should be as close together as possible and
maintained at the same temperature.
Test Circuit for Offset Voltage and its Drift with Temperature
R1
50k*
R3
50k*
R2
100*
V0
15V
–15V
–
+
3
(10)
4
(11)
LT1024
(7)
14
12 (5)
13
(6)
RESISTORS MUST HAVE LOW
THERMOELECTRIC POTENTIAL
THIS CIRCUIT IS ALSO USED AS THE BURN-IN
CONFIGURATION FOR THE LT1024. WITH SUPPLY
VOLTAGES INCREASED TO ±20V, R1 = R3 = 20k,
R2 = 200, AV = 100
VO = 1000V0S
LT1024 AI02
*
**
Teflon is a trademark of Dupont.
APPLICATIO S I FOR ATIO
WU
UU
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