elecTrical characTerisTics The l denotes the specifications which apply over the full o" />
參數(shù)資料
型號(hào): LT1016IS8#PBF
廠商: Linear Technology
文件頁數(shù): 14/20頁
文件大?。?/td> 0K
描述: IC COMPARATOR 10NS HI-SPD 8-SOIC
標(biāo)準(zhǔn)包裝: 100
系列: UltraFast™
類型: 帶鎖銷
元件數(shù): 1
輸出類型: CMOS,補(bǔ)充型,TTL
電壓 - 輸入偏移(最小值): 3mV @ ±5V
電流 - 輸入偏壓(最小值): 10µA @ ±5V
電流 - 輸出(標(biāo)準(zhǔn)): 20mA
電流 - 靜態(tài)(最大值): 35mA
CMRR, PSRR(標(biāo)準(zhǔn)): 96dB CMRR,75dB PSRR
傳輸延遲(最大): 14ns
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
安裝類型: 表面貼裝
包裝: 管件
LT1016
3
1016fc
elecTrical characTerisTics The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V= 5V, VOUT (Q) = 1.4V, VLATCH = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
LT1016C/I
UNITS
MIN
TYP
MAX
VOS
Input Offset Voltage
RS ≤ 100 (Note 2)
1.0
±3
3.5
mV
VOS/T
Input Offset Voltage Drift
4
V/°C
IOS
Input Offset Current
(Note 2)
0.3
1.0
1.3
A
IB
Input Bias Current
(Note 3)
5
10
13
A
Input Voltage Range
(Note 6)
Single 5V Supply
–3.75
1.25
3.5
V
CMRR
Common Mode Rejection
–3.75V ≤ VCM ≤ 3.5V
80
96
dB
PSRR
Supply Voltage Rejection
Positive Supply 4.6V ≤ V+ ≤ 5.4V
LT1016C
60
75
dB
Positive Supply 4.6V ≤ V+ ≤ 5.4V
LT1016I
54
75
dB
Negative Supply 2V ≤ V≤ 7V
80
100
dB
AV
Small-Signal Voltage Gain
1V ≤ VOUT ≤ 2V
1400
3000
V/V
VOH
Output High Voltage
V+ ≥ 4.6V
IOUT =1mA
IOUT = 10mA
2.7
2.4
3.4
3.0
V
VOL
Output Low Voltage
ISINK = 4mA
ISINK = 10mA
0.3
0.4
0.5
V
I+
Positive Supply Current
25
35
mA
I
Negative Supply Current
3
5
mA
VIH
LATCH Pin Hi Input Voltage
2.0
V
VIL
LATCH Pin Lo Input Voltage
0.8
V
IIL
LATCH Pin Current
VLATCH = 0V
500
A
tPD
Propagation Delay (Note 4)
VIN = 100mV, OD = 5mV
10
14
16
ns
VIN = 100mV, OD = 20mV
9
12
15
ns
tPD
Differential Propagation Delay
(Note 4) VIN = 100mV,
OD = 5mV
3
ns
Latch Setup Time
2
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Input offset voltage is defined as the average of the two voltages
measured by forcing first one output, then the other to 1.4V. Input offset
current is defined in the same way.
Note 3: Input bias current (IB) is defined as the average of the two input
currents.
Note 4: tPD and tPD cannot be measured in automatic handling equipment
with low values of overdrive. The LT1016 is sample tested with a 1V step
and 500mV overdrive. Correlation tests have shown that tPD and tPD
limits shown can be guaranteed with this test if additional DC tests are
performed to guarantee that all internal bias conditions are correct. For low
overdrive conditions VOS is added to overdrive. Differential propogation
delay is defined as: tPD = tPDLH – tPDHL
Note 5: Electrical specifications apply only up to 5.4V.
Note 6: Input voltage range is guaranteed in part by CMRR testing and
in part by design and characterization. See text for discussion of input
voltage range for supplies other than ±5V or 5V.
Note 7: This parameter is guaranteed to meet specified performance
through design and characterization. It has not been tested.
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