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參數(shù)資料
| 型號： | LT1011ACN8#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 19/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VOLTAGE COMPARATOR 5V 8-DIP |
| 標準包裝： | 50 |
| 類型： | 通用 |
| 元件數(shù)： | 1 |
| 輸出類型： | 開路集電極 |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 36 V，±1.5 V ~ 18 V |
| 電壓 - 輸入偏移（最小值）： | 0.75mV @ ±15V |
| 電流 - 輸入偏壓（最小值）： | 0.035µA @ ±15V |
| 電流 - 輸出（標準）： | 50mA |
| 電流 - 靜態(tài)（最大值）： | 4mA |
| CMRR, PSRR（標準）： | 115dB CMRR |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 安裝類型： | 通孔 |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1323 (CN2011-ZH PDF) |
LT1011/LT1011A
8
1011afe
For more information www.linear.com/LT1011
applicaTions inForMaTion
Preventing Oscillation Problems
Oscillation problems in comparators are nearly always
caused by stray capacitance between the output and
inputs or between the output and other sensitive pins
on the comparator. This is especially true with high
gain bandwidth comparators like the LT1011, which are
designed for fast switching with millivolt input signals.
The gain bandwidth product of the LT1011 is over 10GHz.
Oscillation problems tend to occur at frequencies around
5MHz, where the LT1011 has a gain of ≈2000. This implies
thatattenuationofoutputsignalsmustbeatleast2000:1at
5MHz as measured at the inputs. If the source impedance
is 1kΩ, the effective stray capacitance between output and
input must have a reactance of more than (2000)(1kΩ) =
2MΩ,orlessthan0.02pF.Theactualinterleadcapacitance
between input and output pins on the LT1011 is less than
0.002pFwhencuttoprintedcircuitmountlength.Additional
stray capacitance due to printed circuit traces must be
minimized by routing the output trace directly away from
input lines and, if possible, running ground traces next
to input traces to provide shielding. Additional steps to
ensure oscillation-free operation are:
1. BypasstheSTROBE/BALANCEpinswitha0.01Fcapaci-
tor connected from Pin 5 to Pin 6. This eliminates stray
capacitive feedback from the output to the BALANCE
pins, which are nearly as sensitive as the inputs.
2. Bypass the negative supply (Pin 4) with a 0.1F ceramic
capacitor close to the comparator. 0.1F can also be
used for the positive supply (Pin 8) if the pull-up load
is tied to a separate supply. When the pull-up load is
tied directly to Pin 8, use a 2F solid tantalum bypass
capacitor.
3. Bypass any slow moving or DC input with a capaci-
tor (≥0.01F) close to the comparator to reduce high
frequency source impedance.
4. Keep resistive source impedance as low as possible. If
a resistor is added in series with one input to balance
source impedances for DC accuracy, bypass it with a
capacitor. The low input bias current of the LT1011
usually eliminates any need for source resistance bal-
ancing. A 5kΩ imbalance, for instance, will create only
0.25mV DC offset.
5. Use hysteresis. This consists of shifting the input offset
voltage of the comparator when the output changes
state.Hysteresisforcesthecomparatortomovequickly
through its linear region, eliminating oscillations by
“overdriving”thecomparatorunderallinputconditions.
Hysteresis may be either AC or DC. AC techniques do
not shift the apparent offset voltage of the compara-
tor, but require a minimum input signal slew rate to be
effective. DC hysteresis works for all input slew rates,
but creates a shift in offset voltage dependent on the
previousconditionoftheinputsignal.Thecircuitshown
in Figure 1 is an excellent compromise between AC and
DC hysteresis.
+
–
+
3
7
1
5
6
8
LT1011
INPUTS
2F
TANT
4
2
–15V
C1
0.003F
0.1F
1011 F01
R2
15M
15V
RL
OUTPUT
Figure 1. Comparator with Hysteresis
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