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參數(shù)資料
| 型號： | LSM2-T/16-W3NG-C |
| 廠商： | CD TECHNOLOGIES INC |
| 元件分類： | 電源模塊 |
| 英文描述： | 1-OUTPUT 52.8 W DC-DC REG PWR SUPPLY MODULE |
| 封裝： | ROHS COMPLIANT PACKAGE-8 |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 1504K |
| 代理商： | LSM2-T/16-W3NG-C |
MDC_LSM2 Series.B01 Page 12 of 17
Technical enquiries email: sales@murata-ps.com, tel: +1 508 339 3000
www.murata-ps.com
LSM2 Series
Single Putput, Non-Isolated
Selectable-Output POL DC/DC Converters
Figure 9. Power Up/Down Sequencing Controller
LSM2 Power Sequencing
Whereas in the old days, one master switch simultaneously turned on the
power for all parts of a system, many modern systems require multiple supply
voltages for different on-board sections. Typically the CPU or microcontroller
needs 1.8 Volts or lower. Memory (particularly DDR) may use 1.8 to 2.5 Volts.
Interface “glue” and “chipset” logic might use +3.3Vdc power while Input/Out-
put subsystems may need +5V. Finally, peripherals use 5V and/or 12V.
Timing is Everything
This mix of system voltages is being distributed by several local power solu-
tions including Intermediate Bus Architecture (IBA) bus converters, Point-of-
load (POL) DC/DC converters and sometimes a linear regulator, all sourced from
a master AC power supply. While this mix of voltages is challenging enough,
a further difficulty is the start-up and shutdown timing relationship between
these power sources and relative voltage differences between them.
For many systems, the CPU and memory must be powered up, boot-strap
loaded and stabilized before the I/O section is turned on. This avoids uncom-
manded data bytes being transferred, compromising an active external network
or placing the I/O section in an undefined mode. Or it keeps bad commands out
of disk and peripheral controllers until they are ready to go to work.
Another goal for staggered power-up is to avoid an oversize load applied to
the master source all at once. A more serious reason to manage the timing and
voltage differences is to avoid either a latchup condition in programmable logic
(a latchup might ignore commands or would respond improperly to them) or a
high current startup situation (which may damage on-board circuits). And on
the power down phase, inappropriate timing or voltages can cause interface
logic to send a wrong “epitaph” command.
Two Approaches
There are two ways to manage these timing and voltage differences. Either the
power up/down sequence can be controlled by discrete On/Off logic controls
for each power supply (see Figure 9). Or the power up/down cycle is set by
Sequencing or Tracking circuits. Some systems combine both methods.
The first system (discrete On/Off controls) applies signals from an already-
powered logic sequencer or dedicated microcontroller which turns on each
downstream power section in cascaded series. This of course assumes all
POL’s have On/Off controls. A distinct advantage of the sequencing controller
is that it can produce an “All On” output signal to state that the full system is
stable and ready to go to work. For additional safety, the sequencer can moni-
tor the output voltages of all downstream POL’s with an A/D converter system.
However the sequencer controller has some obvious difficulties besides
extra cost, wiring and programming complexity. First, power is applied as a
fast-rising, all-or-nothing step which may be unacceptable to certain circuits,
especially large output bypass capacitors. These could force POL’s into over-
current shutdown. And some circuits (such as many linear regulators and some
POL’s) may not have convenient start-up controls. This requires designing and
fabricating external power controls such as high-current MOSFET’s.
If the power up/down timing needs to be closely controlled, each POL must
be characterized for start-up and down times. These often vary—one POL may
stabilize in 15 milliseconds whereas another takes 50 milliseconds. Another
problem is that the sequencing controller itself must be “already running” and
stabilized before starting up other circuits. If there is a glitch in the system,
the power up/down sequencer could get out of step with possible disastrous
results. Lastly, changing the timing may require reprogramming the logic
sequencer or rewriting software.
Sequence/Track Input
A different power sequencing solution is employed on MPS’s LSM2 DC/DC con-
verter. After external input power is applied and the converter stabilizes, a high
impedance Sequence/Track input pin accepts an external analog voltage. The
output power voltage will then track this Sequence/Track input at a one-to-one
ratio up to the nominal set point voltage for that converter. This Sequencing
input may be ramped, delayed, stepped or otherwise phased as needed for
the output power, all fully controlled by the user’s simple external circuits. As a
direct input to the converter’s feedback loop, response to the Sequence/Track
input is very fast (milliseconds).
By properly controlling this Sequence pin, most operations of the discrete
On/Off logic sequencer may be duplicated. The Sequence pin system does not
use the converter’s Enable On/Off control (unless it is a master emergency shut
down system).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LSM2-T30-D12 | 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:DOSA-SMT, 30A POL DC/DC Converters |
| LSM2-T-30-D12-C | 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:DOSA-SMT, 30A POL DC/DC Converters |
| LSM2-T30-D12-C | 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:DOSA-SMT, 30A POL DC/DC Converters |
| LSM2-T-30-D12R-C | 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:DOSA-SMT, 30A POL DC/DC Converters |
| LSM2-T30-D12R-C | 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:DOSA-SMT, 30A POL DC/DC Converters |
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