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參數(shù)資料
| 型號(hào)： | LSIFC929X |
| 英文描述： | LSIFC929X dual channel fibre solutions |
| 中文描述： | LSIFC929X雙通道光纖解決方案 |
| 文件頁(yè)數(shù)： | 43/144頁(yè) |
| 文件大?。?/td> | 1496K |
| 代理商： | LSIFC929X |
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4-3
Table 4.1
describes the PCI Interface signals.
Table 4.1
PCI Interface Signals
Name
BGA Pos
Type
Strength Description
PCICLK
Y11
I
N/A
Clock
provides timing for all transactions on the
PCI bus and is an input to every PCI device. The
LSIFC909 samples all other PCI signals on the
rising edge of PCICLK, and other timing
parameters are defined with respect to this edge.
RST/
V3
I
N/A
Reset
forces the PCI sequencer of the device to
a known state. All 3-state and sustained
3-state signals are forced to a high impedance
state, and all internal logic is reset. The RST/
input is synchronized internally to the rising edge
of PCICLK. The PCICLK input must be active
while RST/ is asserted to properly reset the
device.
GNT/
W1
I
N/A
Grant
indicates to the agent that access to the
PCI bus has been granted. This is a point-to-point
signal. Every master has its own GNT/.
REQ/
W2
O
16 mA
Request
indicates to the system arbiter that this
agent desires use of the PCI bus. This is a point-
to-point signal. Every master has its own REQ/.
REQ64/
Y15
O
16 mA
Request64
indicates that the current bus master
desires to transfer data using 64 bits. REQ64/ is
sampled at the end of reset to indicate the
presence of a 64-bit bus.
ACK64/
AA15
S/T/S
16 mA
Acknowledge64
is an input from the target that
decodes the address, and indicates that the
target is willing to complete a 64-bit transfer. The
LSIFC909 may also assert this signal when
accessed as a slave to complete a 64-bit transfer.
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