參數(shù)資料
型號(hào): LPC3230FET296,551
廠商: NXP Semiconductors
文件頁(yè)數(shù): 55/57頁(yè)
文件大?。?/td> 0K
描述: IC ARM9 MCU 256K 296-TFBGA
特色產(chǎn)品: LPC32x0 ARM926EJ-S Processor
標(biāo)準(zhǔn)包裝: 126
系列: LPC3200
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 266MHz
連通性: EBI/EMI,I²C,IrDA,Microwire,SPI,SSI,SSP,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,電機(jī)控制 PWM,PWM,WDT
輸入/輸出數(shù): 51
程序存儲(chǔ)器類型: ROMless
RAM 容量: 256K x 8
電壓 - 電源 (Vcc/Vdd): 0.9 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 3x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 296-TFBGA
包裝: 托盤
其它名稱: 568-4531
935287119551
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
7 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
C10 SPI1_DATIN/MISO0/GPI_25/
MCI1
C11 GPIO_3/KEY_ROW7/
C13 GPO_8/LCDVD[8][1]
C14 GPI_2/CAP2[0]/
ENET_RXD3[2]
C15 GPI_1/SERVICE
C16 GPI_0/I2S1RX_SDA
C17 KEY_ROW4/ENET_TXD0[2]
C18 KEY_ROW5/ENET_TXD1[2]
Row D
D1
FLASH_RDY
D2
FLASH_ALE
D3
GPO_14
D4
GPO_1
D5
USB_DAT_VP/U5_RX
D6
USB_OE_TP
D7
P0[1]/I2S1RX_WS
D8
GPO_4
D9
GPIO_2/KEY_ROW6/ENET_MDC[2]
D10 GPO_16/MCOB0/LCDENAB[1]/
LCDM[1]
D11 GPO_18/MCOA0/LCDLP[1]
D13 GPI_7/CAP4[0]/MCABORT
D14 PWM_OUT1/LCDVD[16][1]
D15 PWM_OUT2/INTSTAT/LCDVD[19][1]
D18 KEY_COL3/ENET_CRS[2]
Row E
E1
FLASH_IO[3]
E2
FLASH_IO[7]
E3
FLASH_CE
E4
I2C2_SDA
E5
USB_I2C_SCL
E6
USB_I2C_SDA
E7
I2S1TX_SDA/MAT3[1]
E8
GPO_11
E9
GPIO_5/SSEL0/MCI0
E10 GPO_22/U7_HRTS/
LCDVD[14][1]
E11
GPO_10/MCOB2/LCDPWR[1]
E12 GPI_9/KEY_COL7/ENET_COL[2]
E13 GPI_4/SPI1_BUSY
E14 KEY_ROW1/ENET_TXD2[2]
E15 KEY_ROW0/ENET_TX_ER[2]
ENET_REF_CLK[2]
E17 U7_RX/CAP0[0]/
LCDVD[10][1]/GPI_23
E18 U7_TX/MAT1[1]/LCDVD[11][1]
Row F
F1
FLASH_IO[2]
F2
FLASH_WR
F3
FLASH_CLE
F4
GPI_3
F5
VSS_IOC
F6
VSS_IOB
F7
VDD_IOC
F8
VDD_IOB
F9
VDD_IOD
F10 VSS_IOD
F11
VSS_IOD
F12 VSS_IOD
F13 VDD_IOD
F15 KEY_COL0/ENET_TX_CLK[2]
F16 KEY_COL5/ENET_RXD1[2]
F17 U6_IRRX/GPI_21
F18 U5_RX/GPI_20
Row G
G1
EMC_DYCS1
G2
FLASH_IO[5]
G3
FLASH_IO[6]
G4
RESOUT
G5
VSS_IOC
G6
VDD_IOC
G7
VDD_CORE
G8
VSS_CORE
G9
VDD_CORE
G10 VSS_CORE
G11 VDD_CORE
G12 VSS_CORE
G13 U7_HCTS/CAP0[1]/
G14 DBGEN
G15 KEY_COL4/ENET_RXD0[2]
G16 U6_IRTX
G18 JTAG_TMS
Row H
H1
EMC_OE
H2
FLASH_IO[0]
H3
FLASH_IO[1]
H4
FLASH_IO[4]
H5
VSS_IOC
H6
VDD_IOC
H7
VSS_CORE
H12 VSS_IOD
H13 VDD_IOA
H14 JTAG_TCK
H15 U5_TX
Table 3.
Pin allocation table (TFBGA296)
Pin
Symbol
Pin
Symbol
Pin
Symbol
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