參數(shù)資料
型號(hào)： LPC2101FBD48,151
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 8/37頁(yè)
文件大?。?/td> 0K
描述： IC ARM7 MCU FLASH 8K 48-LQFP
產(chǎn)品培訓(xùn)模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
ARM7 Architecture
ARM7 Memory
標(biāo)準(zhǔn)包裝： 250
系列： LPC2100
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 70MHz
連通性： I²C，Microwire，SPI，SSI，SSP，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-LQFP
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 704 (CN2011-ZH PDF)
配用： 568-4310-ND - EVAL BOARD LPC2158 W/LCD
568-4297-ND - BOARD EVAL LPC21XX MCB2100
MCB2103UME-ND - BOARD EVAL MCB2103 + ULINK-ME
MCB2103U-ND - BOARD EVAL MCB2103 + ULINK2
622-1005-ND - USB IN-CIRCUIT PROG ARM7 LPC2K
其它名稱： 568-2092
935280963151
LPC2101FBD48-S
LPC2101_02_03_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 2 June 2009
16 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
6.14 General purpose 16-bit timers/external event counters
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and optionally generate interrupts or perform other actions at
specied timer values, based on four match registers. It also includes three capture inputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing an
application with ‘or’ and ‘a(chǎn)nd’, as well as ‘broadcast’ functions among them.
The LPC2101/02/03 can count external events on one of the capture inputs if the
minimum external pulse is equal or longer than a period of the PCLK. In this conguration,
unused capture lines can be selected as regular timer capture inputs or used as external
interrupts.
6.14.1 Features
Two 16-bit timer/counters with a programmable 16-bit prescaler.
External event counter or timer operation.
Three 16-bit capture channels that can take a snapshot of the timer value when an
input signal transitions. A capture event may also optionally generate an interrupt.
Four 16-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Four external outputs per timer/counter corresponding to match registers, with the
following capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
6.15 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
6.15.1 Features
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
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