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參數(shù)資料
| 型號： | LPC1342FBD48,151 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 9/74頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | LPC13xx |
| 核心處理器： | ARM? Cortex?-M3 |
| 芯體尺寸： | 32-位 |
| 速度： | 72MHz |
| 連通性： | I²C，Microwire，SPI，SSI，SSP，UART/USART，USB |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，WDT |
| 輸入/輸出數(shù)： | 42 |
| 程序存儲器容量： | 16KB（16K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 托盤 |
| 其它名稱： | 568-5214 |
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LPC1311_13_42_43
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 June 2012
17 of 74
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
7.
Functional description
7.1 Architectural overview
The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and
the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the
system bus and are used similarly to TCM interfaces: one bus dedicated for instruction
fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for
simultaneous operations if concurrent operations target different devices.
7.2 ARM Cortex-M3 processor
The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM Cortex-M3 offers many new
features, including a Thumb-2 instruction set, low interrupt latency, hardware multiply and
divide, interruptible/continuable multiple load and store instructions, automatic state save
and restore for interrupts, tightly integrated interrupt controller, and multiple core buses
capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical
Reference Manual which is available on the official ARM website.
7.3 On-chip flash program memory
The LPC1311/13/42/43 contain 32 kB (LPC1313 and LPC1343), 16 kB (LPC1342), or
8 kB (LPC1311) of on-chip flash memory.
7.4 On-chip SRAM
The LPC1311/13/42/43 contain a total of 8 kB (LPC1343 and LPC1313) or 4 kB (LPC1342
and LPC1311) on-chip static RAM memory.
7.5 Memory map
The LPC1311/13/42/43 incorporate several distinct memory regions. Figure 6 shows the
overall map of the entire address space from the user program viewpoint following reset.
The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
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