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參數(shù)資料
| 型號： | LPC1224FBD64/121,1 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 43/61頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 32BIT 48K FLASH 4K 64-LQFP |
| 產品培訓模塊： | LPC1200 Series for Industrial Control |
| 標準包裝： | 160 |
| 系列： | LPC1200 |
| 核心處理器： | ARM? Cortex?-M0 |
| 芯體尺寸： | 32-位 |
| 速度： | 45MHz |
| 連通性： | I²C，IrDA，Microwire，SPI，SSI，SSP，UART/USART |
| 外圍設備： | 欠壓檢測/復位，DMA，POR，WDT |
| 輸入/輸出數(shù)： | 55 |
| 程序存儲器容量： | 48KB（48K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉換器： | A/D 8x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-LQFP |
| 包裝： | 托盤 |
| 其它名稱： | 568-5156 LPC1224FBD64/221 LPC1224FBD64/221,1 |
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LPC122X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 August 2011
48 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
11.5 I2C-bus
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[3]
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
[4]
Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.
[5]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
[6]
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
[7]
The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or
tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If
the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[8]
tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
[9]
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
Table 16.
Dynamic characteristic: I2C-bus pins
Symbol
Parameter
Conditions
Min
Max
Unit
fSCL
SCL clock frequency
Standard-mode
0
100
kHz
Fast-mode
0
400
kHz
Fast-mode Plus
0
1
MHz
tf
fall time
of both SDA and
SCL signals
Standard-mode
-300
ns
Fast-mode
20 + 0.1
C
b
300
ns
Fast-mode Plus
-
120
ns
tLOW
LOW period of the SCL clock
Standard-mode
4.7
-
s
Fast-mode
1.3
-
s
Fast-mode Plus
0.5
-
s
tHIGH
HIGH period of the SCL clock
Standard-mode
4.0
-
s
Fast-mode
0.6
-
s
Fast-mode Plus
0.26
-
s
tHD;DAT
data hold time
Standard-mode
0
-
s
Fast-mode
0
-
s
Fast-mode Plus
0
-
s
tSU;DAT
data set-up time
Standard-mode
250
-
ns
Fast-mode
100
-
ns
Fast-mode Plus
50
-
ns
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