參數(shù)資料
型號(hào): LPC11U24FET48/301,
廠商: NXP Semiconductors
文件頁(yè)數(shù): 7/74頁(yè)
文件大?。?/td> 0K
描述: MCU USB 48TFBGA
產(chǎn)品培訓(xùn)模塊: Code Density for LPC11xx
標(biāo)準(zhǔn)包裝: 490
系列: LPC11Uxx
核心處理器: ARM? Cortex?-M0
芯體尺寸: 32-位
速度: 50MHz
連通性: I²C,Microwire,SPI,SSI,SSP,UART/USART,USB
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 40
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TFBGA
包裝: 托盤(pán)
其它名稱(chēng): 568-8522
LPC11U24FET48/301,-ND
LPC11U2X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 2.2 — 11 March 2014
15 of 74
NXP Semiconductors
LPC11U2x
32-bit ARM Cortex-M0 microcontroller
7.3 SRAM
The LPC11U2x contain a total of 8 kB or 10 kB on-chip static RAM memory.
7.4 On-chip ROM
The on-chip ROM contains the boot loader and the following Application Programming
Interfaces (APIs):
In-System Programming (ISP) and In-Application Programming (IAP) support for flash
IAP support for EEPROM
USB API
Power profiles for configuring power consumption and PLL settings
32-bit integer division routines
7.5 Memory map
The LPC11U2x incorporates several distinct memory regions, shown in the following
figures. Figure 6 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB (Advanced High-performance Bus) peripheral area is 2 MB in size and is divided
to allow for up to 128 peripherals. The APB (Advanced Peripheral Bus) peripheral area is
512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either
type is allocated 16 kB of space. This addressing scheme allows simplifying the address
decoding for each peripheral.
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