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參數(shù)資料
| 型號(hào)： | LP62S4096EU-55LLI |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 512K X 8 BIT LOW VOLTAGE CMOS SRAM |
| 中文描述： | 為512k × 8位低電壓CMOS的SRAM |
| 文件頁(yè)數(shù)： | 14/14頁(yè) |
| 文件大?。?/td> | 162K |
| 代理商： | LP62S4096EU-55LLI |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)當(dāng)前第14頁(yè)
LP62S4096E-T Series
(January, 2002, Version 2.0)
9
AMIC Technology, Inc.
Write Cycle 2
(6)
(Chip Enable Controlled)
tWC
Address
tAW
tWR3
(4)
tCW1 , tCW2
tAS1
DIN
tDW
tWHZ7
DOUT
tDH
tWP2
WE
CE2
CE1
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE1 or high CE2 , and a low WE .
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low WE going high to the end of the
Write cycle.
4. If the CE1 low or CE2 high transition occurs simultaneously with the WE low transition or after the WE
transition, outputs remain in a high impedance state.
5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.
6. OE level is high or low.
7. Transition is measured
±500mV from steady state. This parameter is sampled and not 100% tested.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| LP62S4096EU-55LLT | 制造商:AMICC 制造商全稱(chēng):AMIC Technology 功能描述:512K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S4096EU-70LLI | 制造商:AMICC 制造商全稱(chēng):AMIC Technology 功能描述:512K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S4096EU-70LLT | 制造商:AMICC 制造商全稱(chēng):AMIC Technology 功能描述:512K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S4096EV-55LLI | 制造商:AMICC 制造商全稱(chēng):AMIC Technology 功能描述:512K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S4096EV-55LLT | 制造商:AMICC 制造商全稱(chēng):AMIC Technology 功能描述:512K X 8 BIT LOW VOLTAGE CMOS SRAM |
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