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參數(shù)資料
| 型號(hào)： | LP62S2048U-70LLT |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | CAP 2700PF 50V CERAMIC MONO 5% |
| 中文描述： | 256K × 8位低電壓CMOS的SRAM |
| 文件頁(yè)數(shù)： | 3/17頁(yè) |
| 文件大?。?/td> | 190K |
| 代理商： | LP62S2048U-70LLT |
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LP62S2048A-I Series
PRELIMINARY
(June, 2002, Version 0.0)
11
AMIC Technology, Inc.
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
CE1
CE2
DIN
tDH
tDW
(4)
tCW5
tAW
tWR3
WE
DOUT
tWHZ7
tWP2
tCW5
tAS1
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE .
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.
4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
the WE transition, outputs remain in a high impedance state.
5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured
±500mV from steady state. This parameter is sampled and not 100% tested.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LP62S2048U-70LT | CAP 3300PF 50V CERAMIC MONO 5% |
| LP62S2048V-70LI | 256K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S2048X-10LI | 256K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S2048X-10LLI | 256K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S2048X-10LLT | 256K X 8 BIT LOW VOLTAGE CMOS SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LP62S2048U-70LT | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S2048V-10LI | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S2048V-10LLI | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S2048V-10LLT | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S2048V-10LT | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 8 BIT LOW VOLTAGE CMOS SRAM |
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