參數(shù)資料
型號(hào): LP62S2048AX-55LLI
廠(chǎng)商: AMIC Technology Corporation
英文描述: ER 22C 18#16 4#12 SKT PLUG
中文描述: 256K × 8位低電壓CMOS的SRAM
文件頁(yè)數(shù): 4/17頁(yè)
文件大小: 190K
代理商: LP62S2048AX-55LLI
LP62S2048A-I Series
PRELIMINARY
(June, 2002, Version 0.0)
12
AMIC Technology, Inc.
AC Test Conditions
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Time
5 ns
Input and Output Timing Reference Levels
1.5V
Output Load
See Figures 1 and 2
30pF
* Including scope and jig.
CL
TTL
5pF
CL
TTL
Figure 1. Output Load
Figure 2. Output Load for tCLZ1,
tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW
Data Retention Characteristics (TA = -40
°C to 85°C)
Symbol
Parameter
Min.
Max.
Unit
Conditions
VDR1
2.0
3.3
V
CE1
≥ VCC - 0.2V
VDR2
VCC for Data Retention
2.0
3.3
V
CE2
≤ 0.2V,
ICCDR1
-
5**
A
VCC = 2.0V,
CE1
≥ VCC - 0.2V,
VIN
≥ 0V
ICCDR2
Data Retention Current
-
5**
A
VCC = 2.0V,
CE2
≤ 0.2V,
VIN
≥ 0V
tCDR
Chip Disable to Data Retention Time
0
-
ns
tR
Operation Recovery Time
tRC
-
ns
See Retention Waveform
tVR
VCC Rising Time from Data Retention Voltage
to Operating Voltage
5
-
ms
** LP62S2048A-55LLI/70LLI
ICCDR: max.
1
A at TA = 0°C to + 40°C
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