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參數(shù)資料
| 型號： | LP62P16128CV-12LLT |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | SRAM |
| 英文描述： | 128K X 16 BIT LOW VOLTAGE CMOS SRAM |
| 中文描述： | 128K的× 16位低電壓CMOS的SRAM |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 163K |
| 代理商： | LP62P16128CV-12LLT |
LP62P16128C-T Series
PRELIMINARY
(March, 2002, Version 0.0)
14
AMIC Technology, Inc.
48LD CSP ( 6 x 8 mm ) Outline Dimensions
unit: mm
(48TFBGA)
A
1
A
2
A
B
C
D
E
F
G
H
TOP VIEW
Ball#A1 CORNER
SIDE VIEW
C
SEATING PLANE
//
0.25
C
A
(0.36)
A
B
C
D
E
F
G
H
1
2
3
4
5
6
1
2
3
4
5
6
C
0.10
C
S
0.25 S
A B
b (48X)
BOTTOM VIEW
Ball*A1 CORNER
E
1
e
B
e
D1
D
A
0.20(4X)
0.10
C
Dimensions in mm
Symbol
MIN.
NOM.
MAX.
A
1.00
---
1.20
A1
0.20
---
0.30
A2
---
0.53
---
D
5.90
6.00
6.10
E
7.90
8.00
8.10
D1
---
3.75
---
E1
---
5.25
---
e
---
0.75
---
b
0.30
0.35
0.40
Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF
THE SOLDER BALL AND THE BODY EDGE.
4. BALL PAD OPENING OF SUBSTRATE IS
Φ 0.3mm (SMD)
SUGGEST TO DESIGN THE PCB LAND SIZE AS
Φ 0.3mm (NSMD)
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| LP62S16128CV-70LLI | 128K X 16 BIT LOW VOLTAGE CMOS SRAM |
| LP62S16128CV-70LLT | 128K X 16 BIT LOW VOLTAGE CMOS SRAM |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LP62S1024A-I | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S1024AM-55LLT | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S1024AM-70LLT | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S1024A-T | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S1024AU-55LLT | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 8 BIT LOW VOLTAGE CMOS SRAM |
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