參數(shù)資料
型號: LP62E16256E
廠商: AMIC Technology Corporation
英文描述: 256K X 16 BIT LOW VOLTAGE CMOS SRAM
中文描述: 256 × 16位低電壓CMOS的SRAM
文件頁數(shù): 13/15頁
文件大?。?/td> 164K
代理商: LP62E16256E
LP62E16256E-T Series
PRELIMINARY
(July, 2002, Version 0.0)
6
AMIC Technology, Inc.
AC Characteristics (TA = -25
°C to +85°C, VCC = 1.65V to 2.2V)
Symbol
Parameter
LP62E16256E-70LLT
Unit
Min.
Max.
Read Cycle
tRC
Read Cycle Time
70
-
ns
tAA
Address Access Time
-
70
ns
tACE
Chip Enable Access Time
-
70
ns
tBE
Byte Enable Access Time
-
70
ns
tOE
Output Enable to Output Valid
-
35
ns
tCLZ
Chip Enable to Output in Low Z
10
-
ns
tBLZ
Byte Enable to Output in Low Z
10
-
ns
tOLZ
Output Enable to Output in Low Z
5
-
ns
tCHZ
Chip Disable to Output in High Z
-
25
ns
tBHZ
Byte Disable to Output in High Z
-
25
ns
tOHZ
Output Disable to Output in High Z
-
25
ns
tOH
Output Hold from Address Change
5
-
ns
Write Cycle
tWC
Write Cycle Time
70
-
ns
tCW
Chip Enable to End of Write
60
-
ns
tBW
Byte Enable to End of Write
60
-
ns
tAS
Address Setup Time
0
-
ns
tAW
Address Valid to End of Write
60
-
ns
tWP
Write Pulse Width
55
-
ns
tWR
Write Recovery Time
0
-
ns
tWHZ
Write to Output in High Z
-
25
ns
tDW
Data to Write Time Overlap
30
-
ns
tDH
Data Hold from Write Time
0
-
ns
tOW
Output Active from End of Write
5
-
ns
Note: tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
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