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參數(shù)資料
| 型號(hào)： | LP62E16256E-T |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 256K X 16 BIT LOW VOLTAGE CMOS SRAM |
| 中文描述： | 256 × 16位低電壓CMOS的SRAM |
| 文件頁數(shù)： | 14/15頁 |
| 文件大?。?/td> | 164K |
| 代理商： | LP62E16256E-T |
LP62E16256E-T Series
PRELIMINARY
(July, 2002, Version 0.0)
7
AMIC Technology, Inc.
Timing Waveforms
Read Cycle 1
(1, 2, 4)
tRC
tOH
tAA
tOH
Address
DOUT
Read Cycle 2
(1, 2, 3)
tRC
tAA
Address
tACE
tCHZ5
CE
HB, LB
tBHZ5
OE
tCLZ5
tBE
tBLZ5
tOE
tOLZ5
tOHZ5
DOUT
Notes:
1. WE is high for Read Cycle.
2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL.
3. Address valid prior to or coincident with CE and ( HB and, or LB ) transition low.
4. OE = VIL.
5. Transition is measured
±200mV from steady state. This parameter is sampled and not 100% tested.
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