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參數(shù)資料
| 型號(hào)： | LP62E16128A-T |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | SRAM |
| 英文描述： | 128K X 16 BIT LOW VOLTAGE CMOS SRAM |
| 中文描述： | 128K的× 16位低電壓CMOS的SRAM |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 210K |
| 代理商： | LP62E16128A-T |
LP62E16128A-I Series
PRELIMINARY
(December, 2003, Version 0.0)
15
AMIC Technology, Corp.
Package Information
48LD CSP (6 x 8 mm) Outline Dimensions
unit: mm
(48TFBGA)
A
1
A
2
A
B
C
D
E
F
G
H
TOP VIEW
Ball#A1 CORNER
SIDE VIEW
C
SEATING PLANE
//
0.
25
C
A
(0
.36)
A
B
C
D
E
F
G
H
12
34
56
1
2
3
4
5
6
C
0.10
C
S
0.25 S
A B
b (48X)
BOTTOM VIEW
Ball*A1 CORNER
E
1
e
B
e
D1
D
A
0.20(4X)
0.
10
C
Dimensions in mm
Symbol
MIN.
NOM.
MAX.
A
1.00
1.10
1.20
A1
0.20
0.25
0.30
A2
0.48
0.53
0.58
D
5.90
6.00
6.10
E
7.90
8.00
8.10
D1
---
3.75
---
E1
---
5.25
---
e
---
0.75
---
b
0.30
0.35
0.40
Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF
THE SOLDER BALL AND THE BODY EDGE.
相關(guān)PDF資料 |
PDF描述 |
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| LP62S2048AX-55LLI | ER 22C 18#16 4#12 SKT PLUG |
| LP62S16128B-I | 128K X 16 BIT LOW VOLTAGE CMOS SRAM |
| LP62S2048U-10LI | CAP 1500PF 100V CERAMIC MONO 5% |
| LP62S2048U-10LLI | CAP 1800PF 100V CERAMIC MONO 5% |
| LP62S2048V-70LLI | 256K X 8 BIT LOW VOLTAGE CMOS SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LP62E16128AU-70LLI | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 16 BIT LOW VOLTAGE CMOS SRAM |
| LP62E16128AU-70LLT | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 16 BIT LOW VOLTAGE CMOS SRAM |
| LP62E16128AV-70LLI | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 16 BIT LOW VOLTAGE CMOS SRAM |
| LP62E16128AV-70LLT | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 16 BIT LOW VOLTAGE CMOS SRAM |
| LP62E16256E | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16 BIT LOW VOLTAGE CMOS SRAM |
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