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I
2
C Compatible Interface
I
2
C SIGNALS
The serial interface is in I
2
C mode when IF_SEL = 0. The SCL
pin is used for the I
2
C clock and the SDA pin is used for bidi-
rectional data transfer. Both these signals need a pull-up
resistor according to I
2
C specification. The values of the pull-
up resistors are determined by the capacitance of the bus
(typical resistance is 1.8k). Signal timing specifications are
shown in table I
2
C Timing Parameters.
I
2
C DATA VALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data line
can only be changed when CLK is LOW.
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I
2
C Signals: Data Validity
I
2
C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I
2
C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from LOW
to HIGH while SCL is HIGH. The I
2
C master always generates
START and STOP bits. The I
2
C bus is considered to be busy
after START condition and free after STOP condition. During
data transmission, I
2
C master can generate repeated START
conditions. First START and repeated START conditions are
equivalent, function-wise.
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I
2
C Start and Stop Conditions
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the ac-
knowledge clock pulse. The receiver must pull down the SDA
line during the 9
th
clock pulse, signifying an acknowledge. A
receiver which has been addressed must generate an ac-
knowledge after each byte has been received.
After the START condition, the I
2
C master sends a chip ad-
dress. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W).
The LP5520 address
is 20h when SI=0 and 21h when SI=1.
For the eighth bit, a
“0” indicates a WRITE and a “1” indicates a READ. The sec-
ond byte selects the register to which the data will be written.
The third byte contains data to write to the selected register.
20186151
I
2
C Chip Address
20186136
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = 7-bit chip address, 20h when SI=0 and 21h when SI=1 for LP5520.
I
2
C Write Cycle
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