參數(shù)資料
型號(hào): LP3923TL-VB
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PBGA30
封裝: 3 X 2.50 MM, MICRO SMD-30
文件頁(yè)數(shù): 6/32頁(yè)
文件大?。?/td> 1718K
代理商: LP3923TL-VB
Power Up and Power Down Sequences
30058638
Note 1: CHG_IN is edge sensitive and HF_PWR is level sensitive at startup in STANDBY mode and level sensitive in POWER-ON-RESET mode.
Note 2: PWR_ON is level sensitive at startup. PS_HOLD must be asserted before PWR_ON goes LOW to keep PMU powered. PWR_ON input is not monitored
after PMU is powered up (PS_HOLD asserted).
Note 3: PON_N is a direct inversion of PWR_ON input when LDO3 is powered up (no power-on switch debouncing on PON_N output).
Note 4: The input signal which activates Power Up sequence (either PWR_ON or CHG_IN or HF_PWR) must be on when PS_HOLD is asserted.
Note 5: Time delay between the PS_HOLD going low and the start of Power Down sequence depends on PS_HOLD_DELAY setting (0=35ms, 1=350ms) (typ.).
FIGURE 1. Power Up and Power Down Timing Diagram
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