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參數(shù)資料
| 型號： | LP3918TLX-L |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | Battery Charge Management and Regulator Unit |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PBGA25 |
| 封裝： | 2.50 X 2.50 MM, MICRO, SMD-25 |
| 文件頁數(shù)： | 20/30頁 |
| 文件大?。?/td> | 1292K |
| 代理商： | LP3918TLX-L |
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CONTROL REGISTER WRITE CYCLE
Master device generates start condition.
Master device sends slave address (7 bits) and the data
direction bit (r/w = “0”).
Slave device sends acknowledge signal if the slave
address is correct.
Master sends control register address (8 bits).
Slave sends acknowledge signal.
Master sends data byte to be written to the addressed
register.
Slave sends acknowledge signal.
If master will send further data bytes the control register
address will be incremented by one after acknowledge
signal.
Write cycle ends when the master creates stop condition.
CONTROL REGISTER READ CYCLE
Master device generates a start condition.
Master device sends slave address (7 bits) and the data
direction bit (r/w = “0”).
Slave device sends acknowledge signal if the slave
address is correct.
Master sends control register address (8 bits).
Slave sends acknowledge signal.
Master device generates repeated start condition.
Master sends the slave address (7 bits) and the data
direction bit (r/w = “1”).
Slave sends acknowledge signal if the slave address is
correct.
Slave sends data byte from addressed register.
If the master device sends acknowledge signal, the control
register address will be incremented by one. Slave device
sends data byte from addressed register.
Read cycle ends when the master does not generate
acknowledge signal after data byte and generates stop
condition.
Address Mode
Data Read
<Start Condition>
<Slave Address><r/w = ‘0’>[Ack]
<Register Addr.>[Ack]
<Repeated Start Condition>
<Slave Address><r/w = ‘1’>[Ack]
[Register Date]<Ack or nAck>
… additional reads from subsequent register
address possible
<Stop Condition>
Data Write
<Start Condition>
<Slave Address><r/w = ‘0’>[Ack]
<Register Addr.>[Ack]
<Register Data>[Ack]
… additional writes to subsequent register
address possible
<Stop Condition>
< > Data from master [ ] Data from slave
REGISTER READ AND WRITE DETAIL
20211629
FIGURE 9. Register Write Format
27
www.national.com
LP3918
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LP3919 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CDMA Power Management Unit |
| LP3919RL-A/NOPB | 功能描述:PMIC 解決方案 RoHS:否 制造商:Texas Instruments 安裝風格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| LP3919RL-B/NOPB | 功能描述:PMIC 解決方案 RoHS:否 制造商:Texas Instruments 安裝風格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| LP3919RL-C/NOPB | 功能描述:PMIC 解決方案 RoHS:否 制造商:Texas Instruments 安裝風格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| LP3919RL-D/NOPB | 功能描述:PMIC 解決方案 RoHS:否 制造商:Texas Instruments 安裝風格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
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