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參數(shù)資料
| 型號： | LP3906SQDJXI |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 2 A DUAL SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, QCC24 |
| 封裝： | 5 X 4 MM, 0.80 MM HEIGHT, LLP-24 |
| 文件頁數(shù)： | 14/40頁 |
| 文件大?。?/td> | 4197K |
| 代理商： | LP3906SQDJXI |
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I2C Compatible Serial Interface
I2C SIGNALS
The LP3906 features an I2C compatible serial interface, using
two dedicated pins: SCL and SDA for I2C clock and data re-
spectively. Both signals need a pull-up resistor according to
the I2C specification. The LP3906 interface is an I2C slave that
is clocked by the incoming SCL clock.
Signal timing specifications are according to the I2C bus spec-
ification. The maximum bit rate is 400 kbit/s. See I2C specifi-
cation from Philips for further details.
I2C DATA VALIDITY
The data on the SDA line must be stable during the HIGH
period of the clock signal (SCL), e.g.- the state of the data line
can only be changed when CLK is LOW.
20197816
I2C Signals: Data Validity
I2C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I2C session. START condition is defined as the SDA sig-
nal transitioning from HIGH to LOW while the SCL line is
HIGH. STOP condition is defined as the SDA transitioning
from LOW to HIGH while the SCL is HIGH. The I2C master
always generates START and STOP bits. The I2C bus is
considered to be busy after START condition and free after
STOP condition. During data transmission, I2C master can
generate repeated START conditions. First START and re-
peated START conditions are equivalent, function-wise.
20197817
START and STOP Conditions
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledged related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the ac-
knowledge clock pulse. The receiver must pull down the SDA
line during the 9th clock pulse, signifying acknowledgement.
A receiver which has been addressed must generate an ac-
knowledgement (“ACK”) after each byte has been received.
After the START condition, the I2C master sends a chip ad-
dress. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). Please note that ac-
cording to industry I2C standards for 7-bit addresses, the
MSB of an 8-bit address is removed, and communication ac-
tually starts with the 7th most significant bit. For the eighth bit
(LSB), a “0” indicates a WRITE and a “1” indicates a READ.
The second byte selects the register to which the data will be
written. The third byte contains data to write to the selected
register.
LP3906 has a chip address of 60’h, which is factory pro-
grammed.
20197818
I2C Chip Address
21
www.national.com
LP3906
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LP3906SQ-DJXI | 制造商:Texas Instruments 功能描述:Power Management Unit 24-Pin LLP EP T/R |
| LP3906SQ-DJXI/NOPB | 功能描述:其他電源管理 RoHS:否 制造商:Texas Instruments 輸出電壓范圍: 輸出電流:4 mA 輸入電壓范圍:3 V to 3.6 V 輸入電流: 功率耗散: 工作溫度范圍:- 40 C to + 110 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-48 封裝:Reel |
| LP3906SQE-PPXP/NOPB | 功能描述:其他電源管理 RoHS:否 制造商:Texas Instruments 輸出電壓范圍: 輸出電流:4 mA 輸入電壓范圍:3 V to 3.6 V 輸入電流: 功率耗散: 工作溫度范圍:- 40 C to + 110 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-48 封裝:Reel |
| LP3906SQE-VPFP/NOPB | 功能描述:其他電源管理 RoHS:否 制造商:Texas Instruments 輸出電壓范圍: 輸出電流:4 mA 輸入電壓范圍:3 V to 3.6 V 輸入電流: 功率耗散: 工作溫度范圍:- 40 C to + 110 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-48 封裝:Reel |
| LP3906SQ-FXPI/NOPB | 功能描述:其他電源管理 RoHS:否 制造商:Texas Instruments 輸出電壓范圍: 輸出電流:4 mA 輸入電壓范圍:3 V to 3.6 V 輸入電流: 功率耗散: 工作溫度范圍:- 40 C to + 110 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-48 封裝:Reel |
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