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參數(shù)資料
| 型號： | LP3470M5X-4.38/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5 |
| 封裝： | SOT-23, 5 PIN |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 559K |
| 代理商： | LP3470M5X-4.38/NOPB |
Application Information
RESET TIMEOUT PERIOD
The Reset Timeout Period (t
RP) is programmable using an
external capacitor (C
1) connected to pin SRT of LP3470. A
Ceramic chip capacitor rated at or above 10V is sufficient.
The Reset Timeout Period (t
RP) can be calculated using the
following formula:
t
RP (ms) = 2000 x C1 (F).
For example a C
1 of 100 nF will achieve a tRP of 200 ms. If
no delay due to t
RP is needed in a certain application, the pin
SRT should be left floating.
RESET OUTPUT
In applications like microprocessor (P) systems, errors
might occur in system operation during power-up, power-
down, or brownout conditions. It is imperative to monitor the
power supply voltage in order to prevent these errors from
occurring.
The LP3470 asserts a reset signal whenever the V
CC supply
voltage is below a threshold (V
RTH) voltage. Reset is guar-
anteed to be a logic low for V
CC > 0.5V. Once VCC exceeds
the reset threshold, the reset is kept asserted for a time
period (t
RP) programmed by an external capacitor (C1); after
this interval Reset goes to logic high. If a brownout condition
occurs (monitored voltage falls below the reset threshold
minus a small hysteresis), Reset goes low. When V
CC re-
turns above the reset threshold, Reset remains low for a time
period t
RP before going to logic high.
PULL-UP RESISTOR SELECTION
The LP3470’s Reset output structure is a simple open-drain
N-channel MOSFET switch. A pull-up resistor (R
1) should be
connected to V
CC.
R
1 should be large enough to limit the current through the
output MOSFET (Q
1) below 10 mA. A resistor value of more
than 680
guarantees this. R
1 should also be small enough
to ensure a logic high while supplying all the leakage current
through the Reset pin. A resistor value of less than 68k
satisfies this condition. A typical pull-up resistor value of 20
k
is sufficient in most applications.
NEGATIVE-GOING V
CC TRANSIENTS
The LP3470 is relatively immune to short duration negative-
going V
CC transients (glitches). The Typical Operating Char-
acteristics show the Maximum Transient Duration vs. Nega-
tive Transient Amplitude (graph titled Transient Rejection),
for which reset pulses are not generated. This graph shows
the maximum pulse width a negative-going V
CC transient
may typically have without causing a reset pulse to be
issued. As the transient amplitude increases (i.e. goes far-
ther below the reset threshold), the maximum allowable
pulse width decreases. A 0.1 F bypass capacitor mounted
close to V
CC provides additional transient immunity.
Timing Diagram
10001604
LP3470
www.national.com
6
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