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參數(shù)資料
| 型號： | LMX9402BL1701X |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 1760 MHz, CBGA25 |
| 封裝： | 0.560 X 0.560 X 0.220 INCH, CBGA-25 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 152K |
| 代理商： | LMX9402BL1701X |
Connection Diagram
Pin Descriptions
Pin No.
Pin
Name
I/O
Description
1,2,3,4,5
GND
—
Ground.
6
LD
O
Multiplexed output of the RF programmable dividers, reference dividers, or RF Lock
Detect. Normally used as RF Lock Detect.
7
GND
—
Ground.
8V
CC1
—
Power supply voltage input to PLL.
9
GND
—
Ground.
10
RFOUT
O
VCO Frequency Output.
11, 12
GND
—
Ground.
13
V
CC2
—
Power supply voltage input to VCO
14, 15,
16
GND
—
Ground.
17
Data
I
Binary serial data input. Data entered MSB first. LSB is control bit. High impedance
CMOS input.
18, 19,
20
GND
—
Ground.
21
OSC
IN
I
Reference Oscillator input.
22
CLK
I
High impedance CMOS Clock input. Data is clocked in on the rising edge, into the
various counters and registers.
23
LE
I
Load Enable input (with internal pull-up resistor). When LE Load Enable transitions
HIGH, data stored in the shift registers is loaded into the appropriate latch (control bit
dependent). Clock must be low when LE toggles high or low.
24, 25
GND
—
Ground.
DS200075-2
Top View 25-Pin CBGA Package
See NS Package Number SB25A
LMX9402
www.national.com
2
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