參數(shù)資料
型號(hào): LMX2515LQX0701
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: PLLatinum⑩ Frequency Synthesizer System with Integrated VCO
中文描述: PLL FREQUENCY SYNTHESIZER, 26 MHz, QCC28
封裝: 5 X 5 MM, 0.75 MM HEIGHT, LLP-28
文件頁(yè)數(shù): 13/17頁(yè)
文件大小: 251K
代理商: LMX2515LQX0701
Programming Description
(Continued)
R0 REGISTER
The R0 register address bits (R0 [1:0]) are “00”.
The Rx/Tx bit selects between receive and transmit modes and, in conjunction with the RF VCO selection bit (RF_SEL), the
channel spacing to be synthesized.
The RF_PD bit selects the power down mode of the RF PLL and selected VCO.
The HS bit selects between normal and high speed locking mode.
The RF_SEL bit is set to "0" for the LMX2515LQ0701 and "1" for the LMX2515LQ1321.
The RF N counter consists of the 4-bit programmable counter (RF_B counter), the 3-bit swallow counter (RF_A counter) and the
10-bit delta sigma modulator (RF_FN counter). The equations for calculating the counter values are presented below.
R0 REGISTER
R
MSB
23
SHIFT REGISTER BIT LOCATION
16
15
14
13
Data Field
LSB
0
22
21
20
19
18
17
12
11
10
9
8
7
6
5
4
3
2
1
Address
Field
0
R0
(Default)
RX/
TX
RF_
PD
HS
0
RF_
SEL
RF_B
[3:0]
RF_A
[2:0]
RF_FN
[9:0]
0
Name
RX/TX
Functions
RX/TX Mode
0 = Rx
1 = Tx
Power Down of RF Synthesizer
0 = RF synthesizer on (Active mode)
1 = RF synthesizer powered down
Locking Mode
0 = Normal Mode
1 = High Speed Mode
RF VCO Selection
0 = LMX2515LQ0701
1 = LMX2515LQ1321
RF_B Counter
4-bit programmable counter
0
RF_B
15 for both bands
RF_A Counter
3-bit swallow counter
0
RF_A
7 for LMX2515LQ1321
0
RF_A
3 for LMX2515LQ0701
RF_FN Counter
10-bit modulus counter
0
RF_FN
<
FD See
Table 6
for FD values.
RF_PD
HS
RF_SEL
RF_B [3:0]
RF_A [2:0]
RF_FN [9:0]
Counter Name
Modulus Counter
Programmable Counter
Swallow Counter
Symbol
RF_FN
RF_B
RF_A
Functions
RF N Divider
N = 8 x RF_B + RF_A + RF_FN/FD (LMX2515LQ1321)
N = 4 x RF_B + RF_A + RF_FN/FD (LMX2515LQ0701)
L
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