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參數(shù)資料
| 型號(hào)： | LMX2487ESQX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 7500 MHz, PQCC24 |
| 封裝： | 4 X 4 MM, 0.80 MM HEIGHT, LLP-24 |
| 文件頁數(shù)： | 26/38頁 |
| 文件大小： | 419K |
| 代理商： | LMX2487ESQX |
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2.1 R0 REGISTER
Note that this register has only one control bit, so the N counter value to be changed with a single write statement to the PLL.
REGISTER
R0
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA[22:0]
C0
0
RF_N[10:0]
RF_FN[11:0]
2.1.1 RF_FN[11:0] -- Fractional Numerator for RF PLL
Refer to section 2.6.1 for a more detailed description of this control word.
2.1.2 RF_N[10:0] -- RF N Counter Value
The RF N counter contains an 16/17/20/21 and a 32/33/36/37 prescaler. The N counter value can be calculated as follows:
N = RF_P·RF_C + 4·RF_B + RF_A
RF_C
≥
Max{RF_A, RF_B} , for N-2
FM
-1 ... N+2
FM
is a necessary condition. This rule is slightly modified in the case where the
RF_B counter has an unused bit, where this extra bit is used by the delta-sigma modulator for the purposes of modulation. Consult
the tables below for valid operating ranges for each prescaler.
Operation with the 16/17/20/21 Prescaler (RF_P=0)
RF_N
RF_N [10:0]
RF_C [5:0]
RF_B [2:0]
RF_A [1:0]
<49
49-63
N Values Below 49 are Illegal.
Legal Divide Ratios are:
2nd Order Modulator: 49-61
3rd Order Modulator: 51-59
4th Order Modulator: 55
Legal Divide Ratios are:
2nd and 3rd Order Modulator: All
4th Order Modulator: 64-75
0
1
.
.
1
1
N values above 1023 are prohibited.
64-79
80
...
0
.
1
0
.
1
0
.
1
1
.
1
0
0
0
0
.
1
0
.
1
0
.
1
0
.
1
1023
>1023
Operation with the 32/33/36/37 Prescaler (RF_P=1)
RF_N
RF_N [10:0]
RF_C [5:0]
RF_B [2:0]
RF_A [1:0]
<97
97-226
N Values Below 97 are Illegal.
Legal Divide Ratios are:
2nd Order Modulator: 97-109, 129-145, 161-181, 193-217, 225-226
3rd Order Modulator: 99-107, 131-143, 163-179, 195-215
4th Order Modulator: 103, 135-139, 167-175, 199-211
Legal Divide Ratios are:
2nd and 3rd Order Modulator: All
4th Order Modulator: None
0
1
1
1
.
.
.
.
1
1
1
1
Possible with a second or third order delta-sigma engine.
Possible only with a second order delta-sigma engine.
N values greater than 2045 are prohibited.
227--230
231
...
2039
0
.
1
0
.
1
0
.
1
0
.
0
1
.
1
1
.
1
1
.
1
2040-2043
2044-2045
>2045
www.national.com
26
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2487ESQX/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2487SQ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:3.0 GHz - 6.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum? Frequency Synthesizers with 3.0 GHz Integer PLL |
| LMX2487SQ/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2487SQX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:3.0 GHz - 6.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum? Frequency Synthesizers with 3.0 GHz Integer PLL |
| LMX2487SQX/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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