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參數(shù)資料
| 型號： | LMX2486 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 1.0 GHz - 4.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum TM Frequency Synthesizers with 3.0 GHz Integer PLL |
| 中文描述： | 1.0千兆赫- 4.5吉赫高性能Δ-Σ低功耗雙PLLatinum商標頻率合成器與整數(shù)的3.0 GHz鎖相環(huán) |
| 文件頁數(shù)： | 36/37頁 |
| 文件大?。?/td> | 870K |
| 代理商： | LMX2486 |
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Programming Description
(Continued)
2.8 R7 REGISTER
REGISTER 23 22 21 20 19 18 17 16 15 14
13
12 11 10 9 8
Data[19:0]
1
7
6
5
4
3
2
1
0
C3 C2 C1 C0
1
1
R7
0
0
0
0
0
0
0
0
0
0 DIV4 0
0 0 0 IF_RST RF_RST IF_CPT RF_CPT
1
1
2.8.1 DIV4 -- RF Digital Lock Detect Divide By 4
Because the digital lock detect function is based on a phase error, it becomes more difficult to detect a locked condition for larger
comparison frequencies. When this bit is enabled, it subdivides the RF PLL comparison frequency (it does not apply to the IF
comparison frequency) presented to the digital lock detect circuitry by 4. This enables this circuitry to work at higher comparison
frequencies. It is recommended that this bit be enabled whenever the comparison frequency exceeds 20 MHz and RF digital lock
detect is being used.
2.8.2 IF_RST -- IF PLL Counter Reset
When this bit is enabled, the IF PLL N and R counters are reset, and the charge pump is put in a TRI-STATE condition. This
feature should be disabled for normal operation. Note that a counter reset is applied whenever the chip is powered up via software
or CE pin.
IF_RST
0 (Default)
1
IF PLL N and R Counters
Normal Operation
Counter Reset
IF PLL Charge Pump
Normal Operation
TRI-STATE
2.8.3 RF_RST -- RF PLL Counter Reset
When this bit is enabled, the RF PLL N and R counters are reset and the charge pump is put in a TRI-STATE condition. This
feature should be disabled for normal operation. This feature should be disabled for normal operation. Note that a counter reset
is applied whenever the chip is powered up via software or CE pin.
RF_RST
0 (Default)
1
RF PLL N and R Counters
Normal Operation
Counter Reset
RF PLL Charge Pump
Normal Operation
TRI-STATE
2.8.4 RF_TRI -- RF Charge Pump TRI-STATE
When this bit is enabled, the RF PLL charge pump is put in a TRI-STATE condition, but the counters are not reset. This feature
is typically disabled for normal operation.
RF_TRI
0 (Default)
1
RF PLL N and R Counters
Normal Operation
Normal Operation
RF PLL Charge Pump
Normal Operation
TRI-STATE
2.8.5 IF_TRI -- IF Charge Pump TRI-STATE
When this bit is enabled, the IF PLL charge pump is put in a TRI-STATE condition, but the counters are not reset. This feature
is typically disabled for normal operation.
IF_TRI
0 (Default)
1
IF PLL N and R Counters
Normal Operation
Normal Operation
IF PLL Charge Pump
Normal Operation
TRI-STATE
L
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|---|---|
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| LMX2487ESQX | 7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2486EVAL | 功能描述:時鐘和定時器開發(fā)工具 LMX2486 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| LMX2486SQ | 制造商:Texas Instruments 功能描述:PLL Frequency Synthesizer Dual 5MHz to 4500MHz 24-Pin LLP EP T/R |
| LMX2486SQ/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2486SQX | 制造商:Texas Instruments 功能描述:PLL Frequency Synthesizer Dual 5MHz to 4500MHz 24-Pin LLP EP T/R |
| LMX2486SQX/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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