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參數(shù)資料
| 型號： | LMX2371 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinum Dual Frequency Synthesizer for RF Personal Communications(PLLatinum技術用于射頻個人通訊的雙通道頻率合成器) |
| 中文描述： | PLLatinum雙頻率合成射頻個人通信（PLLatinum技術用于射頻個人通訊的雙通道頻率合成器） |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 516K |
| 代理商： | LMX2371 |
2.0 Programming Description
(Continued)
2.4.4 The FoLD Output Truth Table
Main
R[18]
0
0
1
1
X
X
X
X
0
0
1
Aux
R[18]
0
1
0
1
0
0
1
1
0
1
0
Main
R[19]
0
0
0
0
0
1
0
1
1
1
1
Aux
R[19]
0
0
0
0
1
0
1
0
1
1
1
Fo/LD Output State
Disabled
Aux Lock Detect (Note 10)
Main Lock Detect (Note 10)
Main/Aux Lock Detect (Note 10)
Aux Reference Divider Output
Main Reference Divider Output
Aux Programmable Divider Output
Main Programmable Divider Output
FastLock Output. Open Drain Output (Note 11)
Reset Aux R and N Counters and TRI-STATE Aux Charge Pump (Note 12)
Reset Main R and N Counters and TRI-STATE Main Charge Pump (Note
12)
Reset All Four Counters and TRI-STATE both Charge Pumps (Note 12)
1
1
1
1
X - don’t care condition
Note 10:
Open drain lock detect output is provided to indicate when the VCO frequency is in “l(fā)ock”. When the loop is locked and a lock detect mode is selected,
the pin is HIGH, with narrow pulses LOW. In the Main/Aux lock detect mode a locked condition is indicated when Main and Aux are both locked.
Note 11:
The FastLock mode utilizes the FoLD output pin to switch a second loop filter damping resistor to ground during FastLock operation.Activation of FastLock
occurs whenever the Main loop’s ICP
o
magnitude bit R[16] is selected HI while the R[18] and R[19] mode bits are set.
Note 12:
Aux and Main PLLs can be reset independently from each other by using the R[18] and R[19] bits. The Aux Counter Reset mode resets Aux PLL’s R and
N counters and bringsAux charge pump output to TRI-STATE condition. The Main Counter Reset mode resets Main PLL’s R and N counters and brings Main charge
pump output to a TRI-STATE condition. The Aux and Main Counter Reset modes reset all counters and bring both charge pump outputs to a TRI-STATE condition.
Upon removal of the Reset bits, the N counter resumes counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle.)
2.5 Serial Data Input Timing
Serial Data Input Timing
DS101026-6
NOTES:
Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
TEST CONDITIONS:
The Serial Data Input Timing is tested using a symmetrical waveform around V
CC
/2. The test waveform has an edge rate of 0.6 V/ns with
amplitudes of 2.2V
@
V
CC
= 2.7V and 2.6V
@
V
CC
= 5.5V.
L
www.national.com
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2371 WAF | 制造商:Texas Instruments 功能描述: |
| LMX2371SLBX | 功能描述:IC FREQ SYNTH DUAL 24LAMINATECSP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| LMX2371TM | 功能描述:IC FREQ SYNTH DUAL 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| LMX2371TMX | 功能描述:IC FREQ SYNTH DUAL 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| LMX2372 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications |
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