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參數(shù)資料
| 型號： | LMX2364TMX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 2.6 GHz PLLatinum Fractional RF Frequency Synthesizer with 850 MHz Integer IF Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2600 MHz, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁數(shù)： | 35/39頁 |
| 文件大?。?/td> | 694K |
| 代理商： | LMX2364TMX |
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Supplemental Information
(Continued)
3.1 PCB LAYOUT CONSIDERATIONS
Power Supply Pins:
For these pins, it is recommended that
these be filtered by taking a series 18 ohm resistor and then
placing two capacitors shunt to ground, thus creating a
lowpass filter.Although theoretically, it makes sense to make
these capacitors as large as possible, the ESR ( Equivalent
Series Resistance ) is greater for larger capacitors. It is
therefore recommended to provide two capacitors of very
different sizes for the best filtering. 0.1 uF and 100 pF are
typical values. The charge pump supply pins in particular are
vulnerable to power supply noise.
High Frequency Input Pins, FinRF and FinIF:
The signal
path from the VCO to the PLL is sensitive to matching and
layout, therefore creating unique challenges fro board lay-
out. It is generally recommended that the VCO output go
through a resistive pad and then through a DC blocking
capacitor before it gets to these high frequency input pins. If
the trace length is sufficiently short (
<
1/10th of a wave-
length ), then the pad may not be necessary, however, a
series resistor of about 39 ohms is still recommended to
isolate the PLL from the VCO. The DC blocking capacitor
should be chosen at least to be 100 pF. It may turn out that
the frequency in this trace is above the self-resonant fre-
quency of the capacitor, but since the input impedance of the
PLL tends to be capacitive, it actually be a benefit to exceed
the self-resonant frequency. The pad and the DC blocking
capacitor should be placed as close to the PLL as possible
Complimentary High Frequency Pins, FinRF* and FinIF*:
These outputs may be used to drive the PLL differentially,
but it is very common to drive the PLL in a single ended
fashion. These capacitors should be chosen such that the
impedance, including the ESR of the capacitor, is as close to
an AC short as possible at the operating frequency of the
PLL. 100 pF is a typical value.
3.2 FASTLOCK AND CYCLE SLIP REDUCTION
CIRCUITRY OPERATION
The LMX2364 has enhanced features for FastLock opera-
tion. When the PLL is switching frequencies, the charge
pump current and comparison frequencies may be adjusted.
The purpose of increasing the charge pump current is to
increase the loop bandwidth. The purpose of reducing the
comparison frequency is to combat cycle slipping. If these
two parameters are not changed by the same ratio, then it is
necessary to switch in a resistor in order to keep the loop
filter optimized. Furthermore, it may be difficult in this case to
keep loop filters of higher than second order well optimized
during FastLock in these cases. The timeout counter con-
trols how long the change in charge pump current and/or
comparison frequency is active. One also needs to realize
that there is a frequency glitch that is caused when any sort
of FastLock or Cycle Slip Reduction is disengaged. This
frequency glitch is application specific. In this case the table
below shows all the possible permutations for using the
FastLock and cycle slip reduction circuitry.
Keep Comparison Frequency
the Same
Classical Fastlock
This mode allows the loop
bandwidth to be increased
during FastLock and then
switched back to normal after
FastLock is disengaged.
Operation Without Fastlock
This mode is essentially not
using fastlock at all.
Decrease Comparison Frequency
(RF Side Only)
CSR/Fastlock Combination
This is the recommended way to use CSR.
If the charge pump gain is used to balance
the change in loop gain due to the lower
comparision frequency, no fastlock resistor
is necessary.
CSR Only
In general, this mode is not recommended,
but it may be practical in some rare
situations.
Increase Charge Pump
Current
Keep Charge Pump Current
the Same
Decrease Charge Pump
Current
Illegal Mode
This mode degrades performance and should never be used.
Note:
If the charge pump current and cycle slip reduction
circuitry are engaged in the same proportion, then it is not
necessary to switch in a FastLock resistor and the loop filter
will be optimized for both normal mode and FastLocking
mode. For third and fourth order filters which have problems
with cycle slipping, this may prove to be the optimal choice of
settings.
L
www.national.com
35
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相關代理商/技術參數(shù) |
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|---|---|
| LMX2364TMX/NOPB | 功能描述:IC FREQ SYNTH 2.6GHZ 24-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| LMX2370 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications |
| LMX2370SLBX | 功能描述:IC FREQ SYNTH DUAL 24LAMINATECSP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| LMX2370SLDX | 功能描述:IC FREQ SYNTH DUAL 24LAMINATECSP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| LMX2370TM | 功能描述:IC FREQ SYNTH DL 2.5GHZ 20TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
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