參數(shù)資料
型號(hào): LMX2347SLBX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: PLLatinum⑩ Frequency Synthesizer for RF Personal Communications
中文描述: PLL FREQUENCY SYNTHESIZER, 2500 MHz, CQCC16
封裝: CSP-16
文件頁數(shù): 19/27頁
文件大?。?/td> 606K
代理商: LMX2347SLBX
OSC
IN
Sensitivity Test Setup
20038413
Notes:
1. Test Conditions: R_CNTR = 1000, LD_OUT = 2, PD = 0.
2. Sensitivity limit is reached when the frequency error of the divided RF input is greater than or equal to 1 Hz.
1.0 Functional Description
The basic phase-lock-loop (PLL) configuration consists of a
high-stability crystal reference oscillator, a frequency synthe-
sizer such as the National Semiconductor LMX2346/7, a
voltage controlled oscillator (VCO), and a passive loop filter.
The frequency synthesizer includes a phase detector, cur-
rent mode charge pump, a programmable reference divider,
and a programmable feedback divider. The VCO frequency
is established by dividing the crystal reference signal down
via the reference divider to obtain a frequency that sets the
comparison frequency. This reference signal, f
r
, is then pre-
sented to the input of a phase/frequency detector and com-
pared with another signal, f
p
, the feedback signal, which was
obtained by dividing the VCO frequency down by way of the
feedback divider. The phase/frequency detector measures
the phase error between the f
and f
signals and outputs
control signals that are directly proportional to the phase
error. The charge pump then pumps charge into or out of the
loop filter based on the magnitude and direction of the phase
error. The loop filter converts the charge into a stable control
voltage for the VCO. The phase/frequency detector’s func-
tion is to adjust the voltage presented to the VCO until the
feedback signal’s frequency and phase match that of the
reference signal. When this “phase-locked” condition exists,
the RF VCO’s frequency will be N times that of the compari-
son frequency, where N is the feedback divider ratio.
20038440
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