參數(shù)資料
型號(hào)： LMX2331UTMX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications
中文描述： PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO20
封裝： 0.173 INCH, PLASTIC, TSSOP-20
文件頁數(shù)： 26/42頁
文件大?。?/td> 3318K
代理商： LMX2331UTMX
Test Setups
(Continued)
LMX233xU f
IN
Sensitivity Test Setup
10136640
The block diagram above illustrates the setup required to
measure the LMX233xU device’s RF input sensitivity level.
The same setup is used for a LMX2330TMEB Evaluation
Board. The IF input sensitivity test setup is similar to the RF
sensitivity test setup. The purpose of this test is to measure
the acceptable signal level to the f
RF input of the PLLchip.
Outside the acceptable signal range, the feedback divider
begins to divide incorrectly and miscount the frequency.
The setup uses an open loop configuration. A power supply
is connected to V
and swept from 2.7V to 5.5V. The IF PLL
is powered down (PWDN IF Bit = 1). By means of a signal
generator, an RF signal is applied to the f
RF pin. The 3 dB
pad provides a 50
match between the PLL and the signal
generator. The OSC
pin is tied to V
. The N value is
typically set to 10000 in Code Loader, i.e. RF N_CNTRB
Word = 156 and RF N_CNTRA Word = 16 for PRE RF Bit =
1 (LMX2330U) or PRE RF = 0 (LMX2331U and LMX2332U).
The feedback divider output is routed to the F
o
LD pin by
selecting the
RF PLL N Divider Output
word (F
o
LD Word =
6 or 14) in Code Loader.AUniversal Counter is connected to
the F
o
LD pin and tied to the 10 MHz reference output of the
signal generator. The output of the feedback divider is thus
monitored and should be equal to f
IN
RF / N.
The f
RF input frequency and power level are then swept
with the signal generator. The measurements are repeated
at different temperatures, namely T
= -40C, +25C, and
+85C. Sensitivity is reached when the frequency error of the
divided RF input is greater than or equal to 1 Hz. The power
attenuation from the cable and the 3 dB pad must be ac-
counted for. The feedback divider will actually miscount if too
much or too little power is applied to the f
RF input.
Therefore, the allowed input power level will be bounded by
the upper and lower sensitivity limits. In a typical application,
if the power level to the f
RF input approaches the sensi-
tivity limits, this can introduce spurs and degradation in
phase noise. When the power level gets even closer to these
limits, or exceeds it, then the RF PLL loses lock.
L
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26
相關(guān)PDF資料
PDF描述
LMX2332USLBX PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications
LMX2332UTM PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications
LMX2332UTMX PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications
LMX2335M PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications
LMX2335TM PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LMX2332 WAF 制造商:Texas Instruments 功能描述:
LMX2332A 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications
LMX2332ATM 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述:
LMX2332ATMX 功能描述:IC FREQ SYNTH DUAL 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
LMX2332L 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinumTM Low Power Dual Frequency Synthesizer for RF Personal Communications
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