參數(shù)資料
型號(hào)： LMX2330USLBX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications
中文描述： PLL FREQUENCY SYNTHESIZER, 2500 MHz, PQCC24
封裝： PLASTIC, CSP-24
文件頁數(shù)： 32/42頁
文件大小： 3318K
代理商： LMX2330USLBX
1.0 Functional Description
(Continued)
1.8.2 Open Drain FastLock Output
The LMX233xU Fastlock feature allows faster loop response
time during lock aquisition. The loop response time (lock
time) can be approximately halved if the loop bandwidth is
doubled. In order to achieve this, the same gain/ phase
relationship at twice the loop bandwidth must be maintained.
This can be achieved by increasing the charge pump current
from 0.95 mA (ID
o
RF Bit = 0) in the steady state mode, to
3.8 mA(ID
o
RF Bit = 1) in Fastlock. When the F
o
LD output is
configured as a FastLock output, an open drain device is
enabled. The open drain device switches in a parallel resis-
tor R2’ to ground, of equal value to resistor R2 of the external
loop filter. The loop bandwidth is effectively doubled and
stability is maintained. Once locked to the correct frequency,
the PLL will return to a steady state condition. Refer to
Section 2.8 F
LD
for details on how to configure the F
o
LD
output to an open drain Fastlock output.
1.8.3 Counter Reset
Three separate counter reset functions are provided. When
the F
LD is programmed to
Reset IF Counters
, both the IF
feedback divider and the IF reference divider are held at their
load point. When the
Reset RF Counters
is programmed,
both the RF feedback divider and the RF reference divider
are held at their load point. When the
Reset All Counters
mode is enabled, all feedback dividers and reference divid-
ers are held at their load point. When the device is pro-
grammed to normal operation, both the feedback divider and
reference divider are enabled and resume counting in ‘close’
alignment to each other. Refer to
Section 2.8 F
o
LD
for more
details.
1.8.4 Reference Divider and Feedback Divider Output
The outputs of the various N and R dividers can be moni-
tored by selecting the appropriate F
o
LD word. This is essen-
tial when performing OSC
in
or f
IN
sensitivity measurements.
Refer to the
Test Setups
section for more details. Refer to
Section 2.8 F
o
LD
for more details on how to route the
appropriate divider output to the F
o
LD pin.
1.9 POWER CONTROL
Each synthesizer in the LMX233xU device is individually
power controlled by device powerdown bits. The powerdown
word is comprised of the
PWDN RF
(
PWDN IF
) bit, in
conjuction with the
TRI-STATE ID
o
RF
(
TRI-STATE ID
o
IF
)
bit. The powerdown control word is used to set the operating
mode of the device. Refer to
Sections 2.4.4, 2.5.4, 2.6.4
,
and
2.7.4
for details on how to program the RF or IF power-
down bits.
When either the RF synthesizer or the IF synthesizer enters
the powerdown mode, the respective prescaler, phase de-
tector, and charge pump circuit are disabled. The D
o
RF (D
o
IF), f
RF (f
IF), and f
RF (f
IF) pins are all forced to a
high impedance state. The reference divider and feedback
divider circuits are held at the load point during powerdown.
The oscillator buffer is disabled when both the RF and IF
synthesizers are powered down. The OSC
pin is forced to
a HIGH state through an approximate 100 k
resistance
when this condition exists. When either synthesizer is acti-
vated, the respective prescaler, phase detector, charge
pump circuit, and the oscillator buffer are all powered up.
The feedback divider, and the reference divider are held at
load point. This allows the reference oscillator, feedback
divider, reference divider and prescaler circuitry to reach
proper bias levels. After a finite delay, the feedback and
reference dividers are enabled and they resume counting in
‘close’ alignment (the maximum error is one prescaler cycle).
The MICROWIRE control register remains active and ca-
pable of loading and latching data while in the powerdown
mode.
Synchronous Powerdown Mode
In this mode, the powerdown function is gated by the charge
pump. When the device is configured for synchronous pow-
erdown, the device will enter the powerdown mode upon
completion of the next charge pump pulse event.
Asynchronous Powerdown Mode
In this mode, the powerdown function is NOT gated by the
completion of a charge pump pulse event. When the device
is configured for asynchronous powerdown, the part will go
into powerdown mode immediately.
TRI-STATE ID
o
0
1
0
1
PWDN
0
0
1
1
Operating Mode
PLL Active, Normal Operation
PLL Active, Charge Pump Output in High Impedance State
Synchronous Powerdown
Asynchronous Powerdown
Notes:
1. TRI-STATE ID
o
refers to either the TRI-STATE ID
o
RF or TRI-STATE ID
o
IF bit .
2. PWDN refers to either the PWDN RF or PWDN IF bit.
L
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