參數(shù)資料
型號(hào): LMX2323
廠商: National Semiconductor Corporation
英文描述: PLLatinum? 2.0 GHz Frequency Synthesizer for RF Personal Communications
中文描述: PLLatinum? 2.0千兆赫頻率合成射頻個(gè)人通信
文件頁(yè)數(shù): 9/12頁(yè)
文件大小: 185K
代理商: LMX2323
2.0 Programming Description
(Continued)
2.3 N REGISTER
If the address bit is LOW (ADDR = 0), when LE is transitioned high, data is transferred from the 18-bit shift register into the 17-bit
N register. The N register consists of the 5-bit swallow counter (A counter), the 10-bit programmable counter (B counter) and the
control word. Serial data format is shown below in 2.3.1 5-Bit Swallow Counter Divide Ratio (A Counter) and 2.3.2 10-Bit
Programmable Counter Divide Ratio (B Counter) The pulse swallow function which determines the divide ratio is described in
section 2.3.3 Pulse Swallow Function
First Bit
17
SHIFT REGISTER BIT LOCATION
10
9
Last Bit
16
15
14
13
12
11
8
7
6
5
4
3
2
1
0
0
NB_CNTR [9:0]
NA_CNTR [4:0]
CTL_WORD [1:0]
DS101362-5
L
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